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{Note: This isn't done yet, let alone proofed!! Stay tuned, and let me know if you're interested. -Aron}
Recommended Checkout and Trouble-Shooting Procedures for the D17B Computer
C. H. Beck
Tulane University
As a result of the current modernization of the Minuteman ICBM force, a quantity of Intertial Guidance Systems (Model NS-10Q), each costing $234,000, have been declared excess by the USAF. Since over 1,000 of these advanced computer systems fropm the LGM 30/Minuteman Missiles are schedules to be declared excess, success of this reuitilization project can effect a savings of nearly a quarter of a billion dollars.
NS-10Q systems contain a D17B computer, the associated stable platform, and power supplies. Detailed specifications for the D17B computer are given in Table 1. It is a small, extremely versatile, multipurpose, serial-binary computer.1 The high degree of reliability and ruggedness of the computer are evidenced by the strict requirements of the weapons system.
Mr. Ray E. Close, System Manager, LGM 30 Systems Management Division, Hill AFB, stated at the first Minuteman Computer Users Group meeting in Anaheim, California, on June 12, 1970, that the average MTBF for the over 1,000 D17B's had exceeded 5.5 years. During the time that the D17B has been operating in the Systems Laboratory at Tulane University, a few failures have occurred. These failures were created by occasional inadvertant, improper procedures when measurements were being taken under difficult circumstances. For normal laboratory operating conditions, the D17B can be powered up and shut down frequently without experiencing malfunctions, as has been the case during the past 15 months of extensive operation in the Systems Laboratory.
Thus, the reliability of the D17B will hopefully reduce the occurrence of equipment breakdowns, the need fortechnical maintenance personnel, and the associated maintenance costs once the system is in operation. This is partly because of the use of high reliability components. Also, since the D17B is available to authorized government agencies and contractors for use on crontracts or grants on a non-reimbursable basis, there will be insignificant cost increase with usage. And, with the assistance of the MCUG, it is expected that many users will take over complete system responsibility including maintenance. It is expected that less-skilled technicians can be trained to provide the necessary service. The very high MTBF of the D17B should be considered when planning a computer system which should not be interrupted.
The following items should be considered in planning for a D17B system.
1. Shipping for the D17B and I/O devices, available through DSA.
2. Interfaces for connecting peripherial I/O devices to the D17B.*
3. 28V dc power supply rated at 19A (25A surge).
4. Air duct and blower.
5. Operator control panel.*
6. Engineering effort and labor for installation and checkout of the D17B.*
7. Software developmetn, trouble-shooting, and maintenance.*
*Available through the Minuteman Computer Users Group.
It is estimated that four man-days are required for preparing the D17B for operation and interfacing it to a Flexowriter. An additional two man-days will be sufficient for checkout of a manual control panel and Flexowriter I/O. Considerable efficiency is possible since a single system design will suffice for the application of several D17B's to similar tasks. The MCUG can assist in this regard. Despite the difficulties of limited documentation during the early phases of this project and the associated frustration, The D17B is now performing useful functions in the Systems Laboratory at minimal cost.
The NS-10Q was located just beneath the payload in the nose cone of the Minuteman I Missile. The D17B computer portion, built by Autonetics, a division of North American Rockwell, occupies 180o of the chassis structure of the NS-10Q as shown in Figure 1. The power supply section occupies the other half of the chassis structure toroid. The outer body skin, which provides the NS-10Q the capability of becoming an integral part of the missile frame, may be unbolted and removed when the NS-10Q is to be used for other purposes. Removal of this body section will have no effect on the operation of the D17B. The D17B is 20 in. high, 5 in. deep, has a 29 in. diameter, and weighs approcimately 62 lbs. Components include approximately 1521 transistors, 6282 diodes, 1116 capacitors, and 5094 resistors. These components are mounted on 75 circuit boards of double-copper-clad, engraved, gold-plated, glass-fiber laminate. They have been coated with polyurethane. The design of the D17B placed a premium on reliability since there is no second chance when an airborne computer controlled mission is executed. 1 Hence, DRL logic was used extensively rather than DTL except where gain was required. Extensive use was made of silicon and mesa-germanium semiconductor devices in this fully sold-state computer. A logic level of 1 or True is represented by approximately -10V, and a 0 or False by approximately 0V.
A 28V dc regulated power supply capable of supplying a 25A starting surge must be provided for operation of the computer. Other required voltages are obtained internally by converting the 28V dc into secondary power using solid-state D17B circuitry. The current drawn from the 28V dc supply will vary from 0 to 25A with a steady-state value of approximately 19A referred to as a full load. The positive terminal of teh 28V dc supply should be connected to terminal E2 on the base structure, and the ground terminal should be connected to E3. The secondary power requirements include 400Hz, 3Ø, and various dc voltages as shown in Figure 2.
Power can be applied for a short time to determine that the memory motor is operational or that a secondary power supply is functioning. The 28V, 400Hz, 3Ø can be checked on TB6-1, 2, 3 which is the connection to the fan on top of the D17B. If this fan has been removed, the lead will be easily accessible.
The secondary dc power supplies can be monitored most conveniently at the checkout connector, J2, on the terminals listed in Table 2.
Continuous operation requires that air be passed through the D17B to maintain an ambient temperature of 77oF±9oF (25oC±5oC). A D17B has been operating in the Systems Laboratory for over 1,000 hours using a blower to circulate room air to effect cooling.
Most of the connections for control signals, instruction and data character inputs, and character outputs and for some of the external discrete inputs are available on the 100-pin umbilical connector which was mounted in the outer body skin. These connections, listed in Table 3, can easily be disconnected and attached to a patch panel.
The D17B was designed primarily to solve real-time inertial guidance and flight control problems associated with the Minuteman I Missile. It has the following general capabilities:
The characteristics of the D17B which will be of specific interest in checkout will be desribed. The breakdown of these characteristics along functional subdivisions as identified in Figure 3 is not intended to infer that these elements exist as separate physical entities.5
Since the D17B is a serial-binary computer, simultaneous access to all the bits of a memory location is not needed either for instructions or data. Hence, the arithmetic registers need not be constructed entirely of flip-flops. Instead, they are in the form of circulating loops in memory as illustrated in Figure 4. The D17B has four double-rank arithmetic registers which are the accumulator (A), lower accumulator (L), instruction register (I), and number register (N). Because (L) is addressable, it can be used as rapid-access storage in addition to performing normal arithmetic functions. There are two additional non-addressable registers, which are used without programmer control, and one 3-bit pseudo-index (phase) register. The functional locations of these registers and looks are illustrated in Figure 5.
The central processing unit (CPU) has I/O access to four rapid-access memory loops of 1, 4, 8, and 16 words in addition to the main memory which is arranged in 21 channels of 128 words each. Two input buffer loops of 4 words each provide additional input capability from memory.
Programmed data channels cause data transfers into the arithmetic registers. All machine functions are processed and interpreted in the CPU. The memory channel address from which the next instruction is to be taken is determined by the location counter. When the CPU is ready to accept another instruction from memory, the address is specified by the channel address stored in the location counter and the sector address specified in the previous instruction.
The index register can modify the operand channel address of one of the multiply instructions. This register also serves as a selector switch for choosing on of two pairs of inputs to one of the incremental pulse-type input loops and for sleecting one of four external positions for each of the three D-A analog voltage outputs.
The accumulator holds the results of all arithmetic operations and servers as an output register for parallel digital data, pulse-type signals, D-A analog voltage outputs, and telemetry data. The lower accumulator is involved in certain arithmetic, input, and logical operations. A real-time clock is provided by internal timing signals derived from the clock channel of the disk memory.6
The delay-type memory is a 6,000 r/min, ferrous-oxide-coated disk as illustrated in Figure 6. The disk is driven by a 400 Hz, 3Ø hysteresis-synchronous motor. Non-return-to-zero recording is used. The addressable memory capacity is 5,454 11-bit (single-precision) or 2,727 24-bit (double-precision) words. The format of these words is shown in Figure 7. Main memory is arranged in 21 channels of128 double-precision words each. These channels are numbered in even octal from 00 to 50.
Main memory channels are non-volatile in the event of a power failure or if the system is shut down. The clock channel contains a permanently recorded 34.5 kHz sinusoidal siganl. Sector information is also permanently recorded on another channel. The total non-destructive readout memory is designed to be completely programmable in conjunction with support equipment.
The addressable memory also includes rapid-access loops of 1, 4, 8, and 16 words, two arithmetic registerrs, and two 4-word input buffer loops for direct data entry. There are two additional non-addressable arithmetic registers. These rapid-access loops and registers are actually reserved memory locations as illustrated in Figure 8.
The memory cycle time is 78 1/8 µs if the memory location is coincident with a read head. This is the time required to read one 24-bit serial word and is defined as one word time. The cycle time for the 1-word registers is one word time. The worst-case cycle times for the 4, 8, and 16-word loops are 4, 4, and 8 word times respectively. The worst-case cycle time for the main memory channels is 128 word times.
Program security or memory protect can be maintained by disabling the write heads to a portion of the memory to effect read-only memory. By enabling these write heads it is possible to perform instruction and address modifiation under program control.8
The program, composed of instructions and data words, is initially punched on cards or paper tape as illustrated in Figure 9, or is recorded on magnetic tape. This program is then entered into memory. Specific console initializing and interactive inputs must be supplied under operator manual control using push buttons and switches to cause logical synchronization, conditioning of logic circuitry, and sequentail state transitions between submodes of computer operation. The console control inputs initially cause the D17B to enter the load/verify mode to prepare for entering the program. These console control inputs and the voltage used in the Systems Laboratory are listed in Table 5.
Instruction and data characters can be read in during the load/verify mode; sequential memory locations are assumed unless a location control character is present. The maximum rate of loading into or comparing with the contents of memory is 100 words/s. This is equivalent to 800 characters/s since each 24-bit word is composed of eight octal characters, as illustrated in Figure 10. Negative data must be represented in two's complement form. Control characters read in during the load/verify mode condition logic circuitry to effect appropriate conputer operation.
Additional data represented by 48 discrete lines can be entered under program control. One of these discrete lines monitors the detector flip-flop, DR, which can be set by an external source; setting DR produces a logic signal that indicates the status of external equipment. This function serves as a hardware interrupt. If DR is set, certain discrete outputs are inhibited. DR can be reset under program control.
Incremental inputs of +1, -1, and 0 can be added to the respective contents of eight memory loations in input loops through direct data entry. These inputs are independent of program control. This capability provides for direct digital integration of eight functions--five of 11-bits each, two of 24-bits each, and one of 48-bits. Variable-increment inputs can also be added to the respective contents of memory locations in input loops through direct data entry. These inputs enter the computer on two sets of three lines. One line indicates the sign, and the other two mutually-exclusive input lines indicate increments of one or four. The state of the phase register determines which of the two pairs of inputs is selected. A pulse-type input can be added to the contents of a specific memory location at the maximum rate of 1000 pulses/s.
The variety of output transfers available from the D17B under program control include 3-bit, 4-bit, or 8-bit parallel data channels, discrete logic signals, pulse-type signals, 24-bit serial words, and analog signals. Parity or verify error outputs are also provided as hardware-controlled features. Specific discrete logic signals are disabled by a hardware interrupt if DR is ON.
With these output features, the D17B can output data to an automatic typewriter, light indicators, audible alarms, and other off-on devices. An array of light indicators can be used to display data in various coded forms. Continuous analog output signals can be monitored on a meter, or a permanent and continuous record can be preserved by using a chart strip recorder. Other peripherial devices can be used to prepare punched cards, punched paper tape, or magnetic tape for subsequent data entry into the D17B or another computer for later processing off-line.11
The location of jacks involved in the functional checkout and trouble-shooting of the D17B are illustrated in Figure 11. All flip-flop monitoring locations are listed in Table 6.
1. G. Lapidus, "A look at minicomputer applications," Control Engineering, pp. 82-91, November 1969.
2. R. L. Hooper and L. D. Amdahl, "Tends in aerospace computers," Datamation, vol 13, pp. 22-26, November 1967.
3. D. O. Baechler, "State of the art of aerospace digital computers, 1962-1967," Computer Group News, vol. 2, pp. 1-12, January 1968.
4. A. S. Buchman, "Aerospace Computers," Advances in Computers, vol. 9, pp. 239-284, 1968.
5. A. Epstein and D. Bessel, "Minicomputers are made of this," Computer Decisions, pp. 10-22, August 1970.
6. D. J. Theis and L. C. Hobbs, "Mini-computers for real-time applications," Datamation, vol. 15, pp. 39-61, March 1969.
7. R. T. Ollivier, "A technique for selecting small computers," Datamation, vol. 16, pp. 141-145, January 1970.
8. R. L. Hooper, "The minicomputer, a programming challenge," Proc. AFIPS 1968 FJCC, part 1, pp. 649-654, 1968.
9. R. Rinder, "The input/output architecture of minicomputers," Datamation, vol. 16, pp. 119-124, May 1970.
10. W. H. Roberts, "Minicomputer architecture," IEEE Computer Group News, vol. 3, pp. 5-9, July/August 1970.
11. F. Gruenberger, "Are small free-standing computers here to stay?" Datamation, vol. 12, pp 67-68, April 1966.
MANUFACTURER:
Autonetics, a Division of North American Rockwell, Inc.
MODEL:
D17B
YEAR:
1962
TYPE:
Serial, synchronous
NUMBER SYSTEM:
Binary, fixed point, 2's complement
LOGIC LEVELS:
0 or False, 0V; 1 or true, -10V
DATA WORD LENGTH (bits):
11 or 24 (double precision)
INSTRUCTION WORD LENGTH (bits):
24
MAXIMUM I/O (words/s):
25,600
NUMBER OF INSTRUCTIONS:
39 types from a 4-bit op code by using five bits of the operand address field for instructions which do not access memory
EXECUTION TIMES:
Add (us):
78 1/8
Multiply (us):
546 7/8 or 1,015 5/8 (double precision)
Divide:
(software)
Note:
Parallel processing such as two simultaneous single precision operations is permitted without additional execution time.
CLOCK CHANNEL:
345.6 kHz
ADDRESSING:
Direct addressing of entire memory
Two-address (unflagged) and three-address (flagged) instructions
MEMORY:
Word Length (bits):
24 plus 3 timing
Type:
Ferrous-oxide-coated NDRO disk
Cycle Time (us):
78 1/8 (minimal)
Capacity (words):
5,454 or 2,727 (double precision)
INPUT/OUTPUT:
Input Lines:
48 digital
Output Lines:
28 digital
12 analog
3 pulse
Program:
800 5-bit char/s
PHYSICAL CHARACTERISTICS:
Dimensions:
20" high, 29" diam.
Power:
28V dc at 25A
Circuits:
DRL and DTL
Double copper clad, gold plated, glass fiber laminate, flexible polyurethane coated circuit boards
SOFTWARE:
Minimal delay coding using machine language
Modular special-purpose subroutines
RELIABILITY:
5.5 years MTBF
Location
Voltage
J2-
3
+28
V dc
-
9
+15
-
13
-1
-
14
-25
-
16
+10
-
17
+25
-
18
-3
-
19
+35
-
20
-10
-
21
-28
-
22
+6
-
23
-35
-
24
-5
Pin
Function
1
I1C
Character Input
2
I2C
3
I3C
4
I4C
5
Parity
6
Timing Prime TC'
7
Precision Time Pulse
9
SC1O
Character Output
10
SC2O
11
SC3O
12
SC4O
14
Parity Bit
15
Timing
13
Parity or Verify Error, PVEC
23
Disable Discrete, DDC
90
Master Reset, MRC
91
Halt Prime, KHC'
93
Enable Write, EWC
96
X1C
Discrete Inputs
97
X2C
98
X3C
99
X4C
95
V5C
94
V6C
Numeric Code
Code
Description
00
20,
s
SAL
Split accumulator left shift
00
22,
s
ALS
Accumulator left shift
00
24,
s
SLL
Split left word left shift
00
26,
s
SLR
Split left word right shift
00
30,
s
SAR
Split accumulator right shift
00
32,
s
ARS
Accumulator right shift
00
34,
s
SRL
Split right word left shift
00
36,
s
SRR
Split right word right shift
00
60,
s
COA
Character output A
04
c,
s
SCL
Split compare and limit
10
c,
s
TMI
Transfer on minus
20
c,
s
SMP
Split multipluy/td>
24
c,
s
MPY
Multiply
30
c,
s
SMM
Split multiply modified
34
c,
s
MPM
Multiply modified
40
02,
s
BOC
Binary output C
40
10,
s
BOA
Binary output A
40
12,
s
BOB
Binary output B
40
20,
s
RSD
Reset detector
40
22,
s
HPR
Halt and Proceed
40
26,
s
DOA
Discrete output A
40
30,
s
VOA
Voltage output A
40
32,
s
VOB
Voltage output B
40
34,
s
VOC
Voltage output C
40
40,
s
ANA
And to accumulator
40
44,
s
MIM
Minus magnitude
40
46,
s
COM
Complement
40
50,
s
DIB
Discrete input B
40
52,
s
DIA
Discrete input A
40
60,
s
HFC
Halt fine countdown
40
7-,
s
LPR
Load phase register
44
c,
s
CLA
Clear and Add
50
c,
s
TRA
Transfer
54
c,
s
STO
Store accumulator
60
c,
s
SAD
Split add
64
c,
s
ADD
Add
70
c,
s
SSU
Split subtract
74
c,
s
SUB
Subtract
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