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GREEN BINDER NO LABEL ADMINISTRATIVE PROCEDURE A-2 EIC 4/21/69 QUATSE "ENGINEERING INVENTORY CONTROL" A-3 AOP 4/21/69 QUATSE "ASSEMBLY OR PART NUMBERING SYSTEM" A-7 TE 6/2/69 HANDELMAN "TECHNICIAN EXAMINATION" A-8 PCP - OSTERHOUT "PURCHASE ORDER PREPARATION" A-10 EP 8/1/69 QUATSE "POLICY FOR ENINEERING PURCHASES" A-11 SM 10/1/69 HARRISON "SUPERVISOR'S MANUAL" A-12 MOP 4/2/70 CLARK/KORHONEN "MATERIAL ORDERING FOR PROJECTS" --- BLUE BINDER "INTERNAL DOCUMENTATION MANUAL" MANUAL M-1.2 SPL 11/3/69 LAMPSON "SPL REFERENCE MANUAL" M-2 MPACC 5/8/69 THACKER "MICROPROCESSOR ADDER/CYCLER CARD" M-3.1 MPCLC 1/2/69 THACKER "MICROPROCESSOR CONTROL LOGIC CARD" M-7 MISPS 9/1/69 FREEMAN "MCALLS ON THE MODEL I SUB-PROCESS SYSTEM" M-8 MICRO 9/2/69 LEWENDAL "MICRO REFERENCE AND USER MANUAL" --- GREEN BINDER "INTERNAL DOCUMENTATION MANUAL" MANUAL M-9 ROMT 9/10/69 SWEENEY "ROM TESTER DESCRIPTION AND OPERATION" M-10 PREP 10/8/69 DOVE "PHASE ONE PREPROCESSOR INTERFACE" M-11 UPREP 10/8/69 DOVE "PHASE ONE UNPREPROCESSOR INTERFACE" M-12 CSED 10/15/69 DEUTSCH/DOVE "M1CS PHASE ONE LANGUAGE EDITOR" M-13 PIG 10/28/69 HECKEL "INTERACTIVE MICROPROCESSOR SIMULATOR" M-15 AKOCS 11/30/69 HECKEL "CHARACTER SETS" M-16 PTES 12/9/69 HECKEL "PAPER TAPE READING AND PUNCHING" M-17 PCNR 12/9/69 HECKEL "CHIO PHASE 1 TEST ROUTINES" M-18.1 M30T 8/30/70 THOMPSON "MODEL 30 TRIVIA" M-19 PMS 1/21/70 FREEMAN "PROCESS MEMORY SYSTEM" M-20 DCODT 5/19/70 LAMPSON "DCODT REFERENCE MANUAL" M-21 RPASS 7/22/70 BEHLING/HECKEL "THE REMOTE PROCESSOR ASSEMBLER" M-22 WL 10/19/70 GOODRICH "WIRELISTING" --- GREEN BINDER NO LABEL REPORT R-2 TRGEN 11/3/69 DEUTSCH/DOVE "M1CS PHASE ONE TREE GENERATOR" R-3 SPLGR 12/10/69 LAMPSON "SPL GRAMMAR AND PRECEDENCE" R-4 OPREC 12/16/69 LAMPSON "SUPPORT SOFTWARE FOR OPERATOR PRECEDENCE PARSING" R-5 GELAI 12/17/69 DOVE "GE LEXICAL ANALYZER IMPLEMENTATION" R-8 GEFEQV 3/26/70 DOVE "GE FORTRAN EQUIVALENCE ALGORITHM" --- RED BINDER "INTERNAL DOCUMENTATION DO NOT REMOVE" SPECIFICATION S-1 CHIOM 5/8/69 THACKER "PHASE I CHARACTER I/O INTERFACE SPECIFICATION" (REPLACED BY NCHIO/S-17) S-2.1 FOO 11/4/69 HECKEL "CHIO/CPU INTERFACE" S-3.1 SCCP 9/2/69 DINSMORE "SYSTEM CONTROL, CLOCKS AND POWER" S-4.1 P1PM 2/10/70 THACKER "THE PHASE 1 PHYSICAL MAP" S-7 M30 7/17/69 THOMPSON "COMMUNICATIONS WITH THE IBM MODEL 30" S-8.3 SR 4/29/70 DINSMORE "SYSTEM REGISTERS" S-10.2 BCCPU1 9/10/69 SIMONYI "SPECIAL AND BRANCH CONDITIONS IN CPU1" S-11 MEMS-1 8/8/69 THACKER "MICROPROCESSOR EXPANDED MEMORY SPECIFICATION" S-13.1 SFBCM 8/29/69 DODGE "SPECIAL FUNCTIONS AND BRANCH CONDITIONS IN THE STANDARD MICROPROCESSOR" S-14 MPPC 9/5/69 THACKER "MICRO-PROCESSOR PARITY CHECKING LOGIC" S-15.1 MSIOI 8/15/69 THACKER "MICRO-SCHEDULER INPUT/OUTPUT INTERFACE" S-16 MPPI 8/29/69 THACKER "MICROPROCESSOR POT/PIN INTERFACE" S-17.1 NCHIO 11/3/69 THACKER "CHIO MULTIPLEXER SPECIFICATION" S-19 M30IS 9/17/69 MARUTANI "MODEL 30 INTERFACE SPECIFICATION" S-20 ROMBA 10/9/69 DODGE "READ ONLY MEMORY BIT ASSIGNMENT" S-21 PIF 10/21/69 BARNES/DEUTSCH "SPECIFICATION OF PROGRAM IMAGE FILES" S-22 COMCON 10/21/69 BARNES "COMMAND WRITING CONVENTIONS" S-23 RC 12/17/69 HECKEL "THE REMOTE CONCENTRATOR DESIGN" S-24 CS 1/5/70 HECKEL "THE COMMUNICATIONS SYSTEM - PHASE II" S-25 INITT 1/6/70 THOMPSON "SYSTEM INITIALIZATION TAPE" S-26 DKBK 1/15/70 LEWENDAL "DISK BACKUP SUBSYSTEM" S-27 TEXTF 1/28/70 DEUTSCH "M1 TEXT FILE STANDARD" S-28 SFBCDC 2/26/70 POWELL "SPECIAL FUNCTIONS AND BRANCH CONDITIONS IN THE DATA COMMUNICATIONS COMPUTER" S-29 DCCROM 3/4/70 POWELL "DATA COMMUNICATIONS COMPUTER ROM BIT ASSIGNMENT" S-30 MULT 4/16/70 COHLER "PHASE 1.5 CPU MULTIPLIER" S-31 SFBCPA 4/20/70 COHLER "SPECIAL FUNCTIONS, BRANCH CONDITIONS, AND PSEUDOSCRATCHPAD ADDRESSES IN CPU 1.5" S-32 BCCDCC 4/20/70 SWEENEY "DATA COMMUNICATIONS COMPUTER" S-33 RPU 5/7/70 HECKEL "THE REMOTE PROCESSOR UNIT" S-34 P1.5PM 5/13/70 SPANNAGEL "THE PHASE 1.5 CPU PHYSICAL MAP" S-36 FSOD 9/25/70 WILFORD "FORMAT OF THE SYSTEM OWNER'S DAEL" --- RED BINDER NO LABEL TECHNICAL T-1.2 PCS 4/14/70 THACKER/MURDOCK "PROCUREMENT STANDARDS FOR PRINTED CIRCUIT BOARDS" T-2 CCAS 7/10/69 THACKER "CABLE CARD ASSEMBLY METHOD" T-5 SSE 8/25/69 BARNES "STANDARD FOR SYNTAX EQUATIONS" T-7.1 TC 10/13/69 COHLER "TRANSISTOR CIRCUITS" T-8.2 TPPSLC 12/18/69 DINSMORE "TEST PROCEDURE UNIT POWER SUPPLIES AND UNIT LOCAL CONTROL BOARDS" T-9 PCBWR 10/23/69 COHLER "PC BOARD & BACKBOARD WIRING RULES" T-12 IIP 11/13/69 QUATSE "INCOMING INSPECTION PROCEDURES" T-13.1 PCFI 11/13/69 QUATSE "PC BOARD FINAL INSPECTION PROCEDURES" T-14 PTDP 5/27/70 PHILPOT "PAINTING, TECHNICAL DATA AND PROCEDURE" T-15 CORE - DINSMORE "PROCEDURE FOR ALIGNMENT OF AMPEX CORE MODULES" --- BLACK BINDER NO LABEL WORKING PAPER W-1 MM1 5/9/69 TUYL "MEMORY MANAGEMENT" W-2 PMTSPT 5/9/69 FREEMAN "MCALLS FOR MANIPULATING PMT AND SPT" ??? "VARIATIONS OF STAND-ALONE DDT FROM SYSTEM DDT" W-3.1 TPDDT 4/24/70 TUYL "TEST PROCESSOR DDT" W-4 FNS - BARNES "SYSTEM I FILE-NAMING SYSTEM" W-5 CWS - FREEMAN "THE CORE WORKING SET" W-6 CMP - BARNES "THE COMMAND PROCESSOR" W-7.1 AUD 10/28/69 BARNES "THE ACCOUNT AND USER DIRECTORIES" W-7 AUD - BARNES "THE ACCOUNT-USER DIRECTORY" W-8 PRUN 6/20/69 LAMPSON "RUNNING A PROCESS" W-9 SCBFS - SCHULZ "SYSTEM CALLS TO THE BASIC FILE SYSTEM" (COVER ONLY) W-10 MIFS 6/4/69 SCHULZ "MODEL 1 FILE SYSTEM" (COVER ONLY) W-11.1 IWS 11/6/69 SCHULZ "INTERRUPT AND WAKE-UP SYSTEM" W-12 CSED 6/20/69 DEUTSCH "PRELIMINARY DESCRIPTION OF THE COMPILER SYSTEM EDITOR" W-13 SPLDS - GREENBERG "SPL COMMAND LANGUAGE AND DEBUGGING SYSTEM" (OBS BY SPLDS/W-17) W-14 USI 6/20/69 LAMPSON "MICRO-SCHEDULER IMPLEMENTATION" W-15.1 SYSP 9/20/69 SCHULZ "SYSTEM PARAMETERS" W-17 SPLDS 9/10/69 GREENBERG/STURGEON "SPL COMMAND LANGUAGE AND DEBUGGING SYSTEM" (NOT ORIG) W-18.2 MPAP 2/18/70 QUATSE "MICRO-PROCESSOR ACCEPTANCE PROCEDURE" W-19 SINIT 9/12/69 BARNES "SYSTEM INITIALIZATION AND ERROR RECOVERY" W-20 CPUINT 8/15/69 LAMPSON "CPU INTERRUPTABLILITY" W-21 SPLEP 8/15/69 LAMPSON "SPL CONVENTIONS FOR SYSTEM-DEFINED ENTRY POINTS" W-22 ITPEX 10/14/69 LAMPSON "EXTERNAL INTERFACES FOR THE INTEGRATED TEST PROCESSOR" W-23 ITPRM 9/11/69 LAMPSON "INTEGRAL TEST PROCESSOR REFERENCE MANUAL" W-24 DFMS 8/25/69 MARUTANI "BRIEF DESCRIPTON OF FAST MEORY SIMULATOR" (COVER ONLY) W-25 SPLAPF 8/15/68 LAMPSON "ALLOCATION AND PROGRAM FORMAT IN SPL" W-26 UTENT 10/1/69 BARNES "THE UTILITY ENTER DIALOG" W-27 BSRA 9/10/69 LAMPSON "BASIC SYSTEM RESOURCE ALLOCATION" W-28 CHIO 9/19/69 SCHULZ "CHIO FUNCTIONS IN BASIC SYSTEM" W-29 SSIN 9/30/69 SCHULZ "SOFTWARE SYSTEM INITALIZATION" W-30 MPREC 9/30/69 LAMPSON "MICROPROCESSOR CRACH PROCEDURES INITALIZATION AND BREAKPOINTS" --- BLACK BINDER "MASTERS WORKING PAPERS 30 TO 50" WORKING PAPER W-31 CIOSUC 10/2/69 BARNES "CONTROL INPUT/OUTPUT STREAMS" W-32 SPLEX 10/14/69 DEUTSCH "SPL EXECUTIVE COMMANDS" W-47 APUD 8/17/70 LAMPSON/TUYL "APU DIAGNOSTIC PROGRAM" W-48 PM 9/14/70 FORD "PROFILE MAINTENANCE" W-49 P2CSS 9/25/70 HECKEL "SOFTWARE FOR THE PHASE 2 COMMUNICATIONS SYSTEM" W-50 TM 9/18/70 FORD "TERMINAL MANAGEMENT" --- BLACK BINDER NO LABEL WORKING PAPER W-33 SPCAP 10/21/69 BARNES "SUB-PROCESS CAPABILITIES" W-34 MNODT 11/5/69 THACKER "MNODT" W-35.1 PTPP 5/19/70 TUYL "PROCEDURES FOR TP PROGRAMS" W-36 PROC 12/4/69 SCHULZ "PROCESSES" W-37 ATNFIC 12/16/69 HECKEL "AN EFFICENT MULTIPLEXING ALGORITHM" W-38 IHTWD 12/16/69 HECKEL "CHIO IMPLEMENTATION PHASE 1" W-39 DITP 12/18/69 LAMPSON "ITP DIAGNOSTIC PROGRAM" W-40 FAROUT 1/6/70 HECKEL "AN ERROR-FREE COMMUNICATIONS LINE" W-41 OHWOW 12/31/69 HECKEL "LOCAL ECHOING IN THE COMMUNICATIONS SYSTEM" W-42 1.5ACC 4/3/70 MARUTANI "PHASE 1.5 CPU ADDER/CYCLER CARD" W-43 DBAMC 1/6/70 TUYL "MICROPROCESSOR DEBUGGER FOR THE AMC" W-44 MPT 2/24/70 SUSSET "MICROPROCESSOR TEST PROGRAM" W-45 TSTX 5/29/70 SIMONYI "CPU TEST PROGRAMS" W-46 SDDTCOM 6/17/70 DEUTSCH "SYSDDT COMMANDS" ---