DC205_SWIFT_Specification_Rev_2
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Title: DC205 SWIFT Specification Rev. 2.0
Date: 2 August 1989
Authors: John DeRoo NKS1-1/E4 DTN 291-7220 LEDS::DEROO
Rob Frame NKS1-1/E4 DTN 291-7219 LEDS::FRAME
Anne Solli NKS1-1/E4 DTN 291-7101 LEDS::SOLLI
Abstract: This document describes the user requirements
for DC205, SWIFT (SII With Integrated Fault-
Tolerance). This chip features high speed
handling of the DSSI protocol through the use
of state machines. Also featured is error
detection capability.
F O R I N T E R N A L U S E O N L Y
Copyright ©1989 by Digital Equipment Corporation
The information in this document is subject to change without
notice and should not be construed as a commitment by Digital
Equipment Corporation. Digital Equipment Corporation assumes
no responsibility for any errors that may occur in this document.
This specification does not describe any program or product
which is currently available from Digital Equipment Corporation
nor does Digital Equipment Corporation commit to implement this
specification in any program or product. Digital Equipment
Corporation makes no commitment that this document accurately
describes any product it might ever make.
DC205 Specification - Rev 2.0 FOR INTERNAL USE ONLY Page 2
1 REV 1.0 INITIAL DRAFT
2 REV 1.1 SECOND PASS CHANGES
1. The first pass of the SWIFT chip allowed selection timeouts
in the range of 0 to 187.5 usec. The second pass of the
SWIFT chip increased the multiplication factor of the Timeout
Register from 12.5 usec to 25.6 usec allowing selection
timeouts in the range of from 0 to 384 usec.
2. The first pass of the SWIFT chip had a selection abort time
of 0 nsec. The second pass of the SWIFT changed the
selection abort time to 25.6 usec as required in the Addendum
to DEC STD 161.
3. The description of the Timeout Register was updated to
reflect the second pass change, in section 5.1.1.3 of the
specification.
4. The description of the buffer count field in the buffer
status word was reworded for clarity, in section 7.3.2 of the
specification.
5. A typo was corrected in section 12.2 of the specification in
which the value written to the DICTRL register for external
loopback testing should have been 0013H instead of 0011H.
6. Additional information regarding SWIFT's monitoring of HP_RDY
was provided in sections 13.3 and 13.4 of the specification.
7. The procedure for adding onto a linked list was changed in
section 7.2.4 of the specification.
3 REV 2.0 FINAL CLEANUP
1. Various typos and Index references cleaned up.
2. An additional timing parameter was added to SWIFT register
read and write cycles. It specifies a minimum time value for
HP_CS deassertion.
3. The description of the selection timeout bits of the Timeout
Register was changed disallowing the 25.6 usec multiplication
factor to be multiplied by any value greater than 6 Hex.
This decreases the selection timeout range from 384 usec to
153.6 usec.
DC205 Specification - Rev 2.0 FOR INTERNAL USE ONLY Page 3
Table of Contents 3 August 1989
CONTENTS
1 REV 1.0 INITIAL DRAFT . . . . . . . . . . . . . . . 2
2 REV 1.1 SECOND PASS CHANGES . . . . . . . . . . . . 2
3 REV 2.0 FINAL CLEANUP . . . . . . . . . . . . . . . 2
CHAPTER 1 INTRODUCTION
1.1 GOALS . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 NON-GOALS . . . . . . . . . . . . . . . . . . . . 1-2
CHAPTER 2 SWIFT OVERVIEW
CHAPTER 3 POSSIBLE CONFIGURATIONS
CHAPTER 4 PIN DESCRIPTION
CHAPTER 5 SWIFT INTERNAL REGISTERS
5.1 REGISTER DEFINITIONS . . . . . . . . . . . . . . . 5-5
5.1.1 Control And Setup Registers . . . . . . . . . . 5-5
5.1.1.1 CSR - Control/Status Register . . . . . . . . . 5-5
5.1.1.2 ID - DSSI ID Register . . . . . . . . . . . . . 5-6
5.1.1.3 TMO - Timeout Register . . . . . . . . . . . . . 5-7
5.1.1.4 BUFSIZ - Buffer Size Register . . . . . . . . . 5-8
5.1.2 DSSI Registers . . . . . . . . . . . . . . . . . 5-9
5.1.2.1 TLP - Target List Pointer . . . . . . . . . . . 5-9
5.1.2.2 ILP - Initiator List Pointer . . . . . . . . . 5-10
5.1.2.3 DSCTRL - DSSI Control And Status Register . . 5-10
5.1.2.4 OOVSIZ<4:0> - Other OVerhead SIZe . . . . . . 5-14
5.1.2.5 ISTAT - Interrupt Status Register . . . . . . 5-15
5.1.3 Diagnostic And Test Registers . . . . . . . . 5-17
5.1.3.1 DDB - DSSI Data Bus . . . . . . . . . . . . . 5-17
5.1.3.2 DCS - DSSI Control Signals . . . . . . . . . . 5-18
5.1.3.3 DICTRL - Diagnostic Control Register . . . . . 5-18
5.2 REGISTER INITIALIZATION VALUES . . . . . . . . . 5-20
CHAPTER 6 DSSI OPERATION
CHAPTER 7 SWIFT OPERATION - USER INTERFACE
7.1 DSSI USER SELECTABLE OPTIONS . . . . . . . . . . . 7-1
7.2 FORMATTING PACKETS AND BUFFERS . . . . . . . . . . 7-2
7.2.1 Overview . . . . . . . . . . . . . . . . . . . . 7-2
7.2.2 General Buffer Format . . . . . . . . . . . . . 7-3
7.2.3 Why SWIFT Has Multiple Data Block Formats . . . 7-6
7.2.3.1 Types Of DSSI Packets . . . . . . . . . . . . . 7-7
DC205 Specification - Rev 2.0 FOR INTERNAL USE ONLY Page 4
Table of Contents 3 August 1989
7.2.3.2 SPT Bit . . . . . . . . . . . . . . . . . . . . 7-7
7.2.3.3 Where To Find The EDC For The Data Block . . . . 7-8
7.2.3.4 Zero-Filling . . . . . . . . . . . . . . . . . . 7-8
7.2.3.5 Other Overhead Size (OOVSIZ) . . . . . . . . . . 7-9
7.2.4 Adding To A Linked List . . . . . . . . . . . . 7-9
7.2.5 Removing From A Linked List . . . . . . . . . 7-10
7.3 SWIFT TO USER - CONTROL/STATUS INFORMATION . . . 7-11
7.3.1 Indicating That The Transfer Is Complete . . . 7-11
7.3.2 Providing Transfer Status - Packet Status Word 7-11
CHAPTER 8 TARGET OPERATION
8.1 TARGET RECEIVING A PACKET - A STEP BY STEP
DESCRIPTION . . . . . . . . . . . . . . . . . . . 8-1
8.2 TARGET COMPLETING A PACKET - 4 MODES . . . . . . . 8-5
8.3 ADDITIONAL NOTES ON TARGET OPERATION . . . . . . . 8-6
8.3.1 Target Timeout . . . . . . . . . . . . . . . . . 8-6
8.3.2 Target Receiving A RST While On The Bus . . . . 8-6
CHAPTER 9 INITIATOR OPERATION
9.1 INITIATOR TRANSFERRING A PACKET - A STEP BY STEP
DESCRIPTION . . . . . . . . . . . . . . . . . . . 9-1
9.2 INITIATOR COMPLETING A PACKET - 3 MODES . . . . . 9-7
9.3 ADDITIONAL NOTES ON INITIATOR OPERATION . . . . . 9-7
9.3.1 Initiator And Fair Arbitration . . . . . . . . . 9-8
9.3.2 Initiator Timeout . . . . . . . . . . . . . . . 9-8
9.3.3 Initiator Receiving A RST While On The Bus. . . 9-8
9.3.4 Initiator Read Back Error Detection . . . . . . 9-8
9.3.5 Initiator Detecting A Selection Timeout . . . . 9-8
CHAPTER 10 DATA INTEGRITY MEASURES
10.1 ERROR PROTECTION ON DSSI BUS . . . . . . . . . . 10-1
10.2 BACKPORT ERROR DETECTION . . . . . . . . . . . . 10-1
10.3 BUFFER PROTECTION . . . . . . . . . . . . . . . 10-2
10.3.1 Rotated XOR For Buffer EDCs . . . . . . . . . 10-2
10.3.1.1 How EDCs Are Calculated . . . . . . . . . . . 10-2
10.3.2 Sync Character Overlapping The Status Word . . 10-3
10.4 SWIFT REGISTER PROTECTION . . . . . . . . . . . 10-3
10.4.1 Read Back . . . . . . . . . . . . . . . . . . 10-4
10.4.2 Register Write Protect . . . . . . . . . . . . 10-4
10.4.3 Address Separation . . . . . . . . . . . . . . 10-4
10.4.4 Sync Characters . . . . . . . . . . . . . . . 10-5
10.4.5 Effects Of Bad Data . . . . . . . . . . . . . 10-5
10.4.5.1 Interrupt Status Register . . . . . . . . . . 10-5
10.4.5.2 DSSI Control Register . . . . . . . . . . . . 10-6
DC205 Specification - Rev 2.0 FOR INTERNAL USE ONLY Page 5
Table of Contents 3 August 1989
CHAPTER 11 ARBITRATING MODE
11.1 ADDITIONAL FUNCTIONALITY . . . . . . . . . . . . 11-1
11.1.1 Memory Arbitration . . . . . . . . . . . . . . 11-1
11.1.2 Address Counter Control . . . . . . . . . . . 11-2
11.1.3 Reduced Address Capability . . . . . . . . . . 11-2
CHAPTER 12 TEST STRATEGY
12.1 LOOP BACK TESTING . . . . . . . . . . . . . . . 12-1
12.1.1 SWIFT As An Initiator . . . . . . . . . . . . 12-2
12.1.2 SWIFT As A Target . . . . . . . . . . . . . . 12-4
12.2 EXTERNAL CONNECTOR TESTING . . . . . . . . . . . 12-5
12.3 OTHER TESTABILITY FEATURES . . . . . . . . . . . 12-6
12.3.1 Test Bit In DICTRL . . . . . . . . . . . . . . 12-6
12.3.2 SRD Bit In DICTRL . . . . . . . . . . . . . . 12-6
12.3.3 LOTC And BC . . . . . . . . . . . . . . . . . 12-7
CHAPTER 13 EXTERNAL OPERATIONS AND TIMING
13.1 MICROPROCESSOR READ CYCLES . . . . . . . . . . . 13-1
13.2 MICROPROCESSOR WRITE CYCLES . . . . . . . . . . 13-3
13.3 MEMORY READ CYCLES (NORMAL MODE) . . . . . . . . 13-6
13.4 MEMORY WRITE CYCLES (NORMAL MODE) . . . . . . . 13-8
13.5 MEMORY READ CYCLES (ARBITRATING MODE) . . . . . 13-10
13.6 MEMORY WRITE CYCLES (ARBITRATING MODE) . . . . . 13-12
CHAPTER 14 MATERIAL SPECIFICATIONS
14.1 PACKAGE . . . . . . . . . . . . . . . . . . . . 14-1
14.2 PINOUT . . . . . . . . . . . . . . . . . . . . . 14-2
14.2.1 Signal Name To Pin Number Mapping . . . . . . 14-2
14.2.2 Pin Name Mapped To IO-Cell Type . . . . . . . 14-3
14.2.3 Power And Ground Pin Requirements . . . . . . 14-4
14.3 POWER CONSUMPTION . . . . . . . . . . . . . . . 14-4
CHAPTER 15 ELECTRICAL SPECIFICATIONS
15.1 DSSI BUS ELECTRICAL SPECIFICATIONS . . . . . . . 15-1
15.2 NON-DSSI BUS ELECTRICAL SPECIFICATIONS . . . . . 15-1
CHAPTER 1
INTRODUCTION
This document is the specification for SWIFT (SII With Integrated
Fault Tolerance), a special purpose, high speed, DSSI interface chip.
This chip contains much of the functionality of the existing SII chip.
In addition, SWIFT provides error detection capability and the ability
to pre-format data for disk drives. This is provided through EDC
generation and checking on the memory port and user-controllable
buffer sizes. The memory port of the SWIFT is modeled after the II
(Integrated circuit Interconnect), which specifies a common protocol
and interface timing to be used for inter-chip communication. The
intent of this document is to define, in detail, the user visible
interface. This includes the memory interface signals and timing, the
internal registers visible to the microprocessor through the memory
interface, and the behavior of the chip during execution.
1.1 GOALS
The goals of SWIFT are simply stated and include:
1. SWIFT should interface to the PHOENIX host port (in adapter
master mode) without any "glue" logic (excepting passive
devices).
2. SWIFT should support both the initiator and target DSSI
roles.
3. SWIFT should implement synchronous data transfers above
4MB/s.
4. SWIFT should use CMOS technology so as not to dissipate more
than 1.0 watt.
5. SWIFT should implement as much DSSI-specific functionality as
possible. It should control the DSSI bus nearly
autonomously.
6. SWIFT should be usable by both the RF disk drive group and
the Cirrus group.
INTRODUCTION Page 1-2
GOALS 3 August 1989
7. SWIFT should include on-board DSSI drivers.
1.2 NON-GOALS
1. SWIFT is not intended to be a generic chip, usable by many
groups.
2. SWIFT is not intended to support SCSI mode.
CHAPTER 2
SWIFT OVERVIEW
SWIFT interfaces two "ports". One is the memory backport. This
includes sixteen multiplexed address/data lines along with an extra
address line, an address strobe, a data strobe, and a ready signal.
This allows direct interface to the Phoenix chip. This port will
allow only address-data-data-data cycles. In other words, the address
is present on the multiplexed address/data lines when the address
strobe is asserted. Following this is a series of data strobes, each
terminated by the receipt of a ready signal. These data strobes
provide data to or expect data from sequential addresses in memory.
This port also allows a microprocessor to interface to SWIFT by
utilizing the same multiplexed address/data lines, along with a chip
select, an address enable and a data enable signal. SWIFT will
respond to the assertion of chip select by asserting the address
enable output. At the deassertion of the signal, SWIFT will latch the
address and direction of the transaction. Following that will be the
data enable output. At the deassertion of this signal, data will be
latched by SWIFT on a write to SWIFT operation or will be available to
the external device on a read from SWIFT.
The second port is the DSSI bus. The outputs from SWIFT are
designed to meet the driver requirements necessary to interface
directly with the DSSI bus. SWIFT will generate and check parity and
support both the initiator and target roles.
CHAPTER 3
POSSIBLE CONFIGURATIONS
There are two planned uses of SWIFT:
1. RFxx Disk Drives - SWIFT fits into the system as follows:
+-----+ +-----+ +-----+
|68000| | ROM | | RAM |
| | | | | |
+--+--+ +--+--+ +--+--+
| | |
+--------+--------+
V
/-----\ +-------+ +-----+
/ DSSI \| SWIFT |<--->| PNX |<----> To Drive
\ /| | | | Electronics
\-----/ +-------+ +-----+
|
V
+-----+
| PNX |
| MEM |
+-----+
In this case, the microprocessor communicates with SWIFT
through the Phoenix (PNX) chip. All DMA transfers are
directed to and from Phoenix memory.
2. Cirrus IO Modules - SWIFT fits into the Cirrus system as
follows:
POSSIBLE CONFIGURATIONS Page 3-2
3 August 1989
+--------+
|FIREWALL|
| |
+--------+
|
V
/-----\ +-------+ +------+
/ DSSI \| SWIFT |<--->| SLIM |<---> to LANCE
\ /| | | |
\-----/ +-------+ +------+
|
V
+------+
| BUF |
| MEM |
+------+
In this case, the microprocessor communicates to SWIFT
through the SLIM chip. All DMA transfers are directed to and
from buffer memory.
CHAPTER 4
PIN DESCRIPTION
To perform all of the required functions, the SWIFT will be in a 68
pin Cerquad package. The pins can be easily divided into three
categories. Two of these correspond to the ports previously
mentioned, namely the DSSI port and the memory port. The third is
classified as miscellaneous, which includes power, test and clock
inputs. The pin descriptions are given below. All signals can be
characterized by a combination of the following signal types:
o (BID) - Bi-directional
o (IN) - Input
o (OUT) - Output
o (OD) - Open Drain Output
o (3S) - Tri-State
DSSI port. The SWIFT interface to the DSSI bus is composed
of the following 19 pins:
1. DSSI_DATA<7:0> L. (BID, OD). DSSI data bus.
2. DSSI_PARITY L. (BID, OD). DSSI parity line.
3. DSSI_CMD L. (BID, OD). DSSI C/D line.
4. DSSI_SEL L. (BID, OD). DSSI SEL line.
5. DSSI_INPUT L. (BID, OD). DSSI I/O line.
6. DSSI_REQ L. (BID, OD). DSSI REQ line.
7. DSSI_ACK L. (BID, OD). DSSI ACK line.
8. DSSI_BSY L. (BID, OD). DSSI BSY line.
PIN DESCRIPTION Page 4-2
3 August 1989
9. DSSI_RST L. (BID, OD). DSSI RST line.
10. ID<2:0> L. (IN). The DSSI ID number. The value on
these pins will be used by SWIFT as its DSSI ID when bit
15 of the ID register is clear (0). At that time, a read
of the ID register will show the active high assertion of
the ID pins as the SWIFT ID. When bit 15 of the ID
register is set, the ID pins are not used and not
readable through SWIFT. The value in the ID register
will be used by SWIFT as its DSSI ID.
Memory Port. The SWIFT interface to the memory port is
composed of the following 26 signals:
1. HP_DAL <15:00> H. (BID, 3S). Multiplexed address/data
lines. During the data portion of the cycle, these
signals represent DATA <15:00>. During the address
portion, they are used to represent ADDRESS <15:01,17>.
HP_ADDR16 represents ADDRESS <16>. This use of HP_DAL
<00> during the address portion of the cycle doubles the
space addressable by SWIFT.
2. HP_ADDR16 H. (OUT, 3S). An extension of the memory
address space addressable by SWIFT. Note that this and
HP_DAL <15:00> allows SWIFT to access 256KB. This signal
is used for address only and is valid only during the
address portion of the bus cycle.
3. HP_WRITE L. (BID, 3S). This signal is asserted to
indicate that the current memory cycle is a WRITE
operation, as seen by the bus master, deasserted
otherwise. During SWIFT register accesses, it is sourced
by external logic, and should be driven following the
assertion of HP_ADREN L; it may be released following the
deassertion of HP_ADREN L; it must be released following
the deassertion of HP_AS.
4. HP_AS L. (OUT, 3S). This signal defines the boundary of
a memory cycle when asserted. Note that HP_DAL
(containing an address) will be valid prior to the
assertion of HP_AS; the assertion of HP_AS is the
latching condition. This signal will remain asserted for
only the first transfer. This signal is also used during
microprocessor accesses to SWIFT. Its deassertion is a
signal to the external logic to stop driving HP_WRITE.
In arbitrating mode and during memory accesses, this
signal is used as a clock input to an external counter.
It is not asserted during microprocessor accesses in this
mode.
5. HP_DS L. (OUT, 3S). This signal is a data strobe, and
is only used when accessing memory. Data must be present
on HP_DAL<15:00> just after the assertion of HP_DS and is
PIN DESCRIPTION Page 4-3
3 August 1989
latched on the trailing edge by SWIFT on read cycles or
by the memory on write cycles.
6. HP_RDY L. (IN). When asserted during the data portion
of a memory cycle, it informs SWIFT that data is ready on
a read operation or that data has been taken on a write
operation and that the current cycle can end. This
signal is not used during microprocessor accesses. In
arbitrating mode, this signal is used as a bus request
signal. SWIFT asserts HP_BUSGRANT in response to the
assertion of this when it has relinquished the HP_DAL
bus.
7. HP_CS L. (IN). This signal is asserted low to indicate
that the microprocessor wishes to access a SWIFT
register. SWIFT will respond to this as soon as the
current bus cycle (if one was in progress) has completed.
This signal, together with the HP_WRITE signal, will
control the direction and enables of the transceivers in
the chip. The HP_CS signal can be deasserted following
the assertion of HP_ADREN.
8. HP_ADREN L. (OUT, 3S). This signal is asserted in
response to a chip select to inform the microprocessor
that the register address may be placed on the HP_DAL
lines. This signal can also act as a bus grant to the
microprocessor. The local intelligence will also drive
HP_WRITE following the assertion of this signal. This
signal is not used during memory accesses.
9. HP_DATAEN L. (OUT, 3S). This signal is asserted when
SWIFT is ready to accept or deliver register data on the
HP_DAL lines. This signal, coupled with HP_WRITE can act
as the enable and direction inputs to an external
transceiver. This signal is not used during memory
accesses.
10. HP_CLK H. (IN). This is the clock input used by SWIFT
to synchronize HP_CS, HP_ADREN and HP_DATAEN. This
allows the designer to use synchronous circuitry, if
desired. If not, this pin may be connected to SYS_CLK.
11. HP_BUSGRANT L. (OUT, 3S). This signal is used only in
the arbitrating mode. Its assertion indicates that SWIFT
has relinquished the memory bus to another device.
Miscellaneous Signals. The 23 miscellaneous signals are:
1. SYS_INTERRUPT L. (OUT, OD). One multi-purpose interrupt
line to the microprocessor to inform it of packet
transfer termination or error conditions. Its assertion
indicates that an interrupt is pending. It will remain
asserted until SWIFT is reset or the ISTAT Register is
PIN DESCRIPTION Page 4-4
3 August 1989
cleared by the microprocessor.
2. SYS_RESET L. (IN). This signal, when asserted, will
force SWIFT to reset all internal state machines,
initialize all registers and disconnect itself from the
DSSI bus.
3. SYS_CLK H. (IN). This is the clock input for SWIFT.
SWIFT requires a 30 MHz, 50(± 5)% duty cycle clock.
4. SYS_TEST H. (IN). SWIFT requires this pin be pulled
down for normal operation. When pulled up SWIFT is in
the test mode and all output pins are in a high impedance
state.
5. TESTOUT H. (OUT). This pin is the output of SWIFT's
parametric NAND tree.
6. QVSS1<4:0>. (GND). Ground return for DSSI drivers.
7. QVSS2 (GND). Ground, used with VBIAS to produce a
voltage reference for the receivers of the DSSI
transceivers.
8. QVDD1 (PWR). The power input for the DSSI transceivers
9. IOVSS<1:0> (GND). Ground return for the host port
drivers on the pad ring.
10. IOVDD<1:0> (PWR). The power input for the host port
drivers on the pad ring.
11. VSS<2:0> (GND). Ground return for the internal logic of
the chip.
12. VDD<2:0> (PWR). The power input for the internal logic
of the chip.
13. VBIAS. Must be tied to 5.62 Kohm 1% bias resistor to
ground. Used for reference voltage generator.
PIN DESCRIPTION Page 4-5
3 August 1989
Pin Summary
_______________________________________
| |
| DSSI Port |
| |
<======>| DSSI_DATA<7:0> |
<------>| DSSI_PARITY |
<------>| DSSI_CMD |
<------>| DSSI_INPUT |
<------>| DSSI_REQ |
<------>| DSSI_ACK |
<------>| DSSI_BSY |
<------>| DSSI_SEL ID<2:0> |O<====
<------>| DSSI_RST |
| |
|_______________________________________|
| |
| Memory Port |
| |
<======>| HP_DAL<15:00> HP_AS |O----->
<-------| HP_ADDR16 HP_DS |O----->
<----->O| HP_WRITE HP_ADREN |O----->
------>O| HP_RDY HP_DATAEN |O----->
------>O| HP_CS BUSGRANT |O----->
------->| HP_CLK |
| |
|_______________________________________|
| |
| Miscellaneous |
| |
------>O| SYS_RESET SYS_INT |O----->
------->| SYS_CLK TESTOUT | ------>
------->| SYS_TEST |
=======>| PWR<5:0> |
=======>| GND<10:0> |
------->| VBIAS |
|_______________________________________|
CHAPTER 5
SWIFT INTERNAL REGISTERS
SWIFT contains fourteen microprocessor-visible registers that are used
to control and monitor the behavior of SWIFT during operation. Five
registers are used to set up SWIFT. Information in these registers
includes ID, timeout values, buffer size, alternate CI overhead size,
and general enables. These registers are typically only accessed at
startup and can be write-protected.
Four registers are used to operate SWIFT. Two of these are
pointer registers. One provides exception notification information
and error flags, and the last is used to enable and monitor the
operation of SWIFT. These will be referred to as "normal use" or DSSI
registers.
The last five registers provide diagnostic capabilities. Two of
them allow direct control of the DSSI bus for diagnostic testing. One
register allows SWIFT to be configured in one of several test modes,
and the remaining registers allow visibility into SWIFT for
diagnostics. These registers are only used to diagnose the
functionality of the chip and should only be accessed during powerup
testing. These registers can also be write-protected.
The register "map" is defined below:
SWIFT INTERNAL REGISTERS Page 5-2
3 August 1989
SWIFT REGISTER MAP (USER VISIBLE)
HP_DAL<5:0> DATA BUS NAME
15 0
+-------------------------------+
+00 | CONTROL/STATUS REGISTER | CSR
+-------------------------------+
+02 | ID REGISTER | ID
+-------------------------------+
+04 | TIMEOUTS | TMO
+-------------------------------+
+06 | BUFFER SIZE REGISTER | BUFSIZ
+-------------------------------+
+08 | TARGET LIST POINTER | TLP
+-------------------------------+
+10 | BLANK |
+-------------------------------+
+12 | BLANK |
+-------------------------------+
+14 | INITIATOR LIST POINTER | ILP
+-------------------------------+
+16 | BLANK |
+-------------------------------+
+18 | DSSI CONTROL | DSCTRL
+-------------------------------+
+20 | INTERRUPT STATUS | ISTAT
+-------------------------------+
+22 | DSSI DATA BUS AND PARITY | DDB
+-------------------------------+
+24 | DSSI CONTROL SIGNALS | DCS
+-------------------------------+
+26 | DIAG. CONTROL REGISTER | DICTRL
+-------------------------------+
+28 | OTHER OVERHEAD SIZE REGISTER | OOVSIZ
+-------------------------------+
+30 | BLANK |
+-------------------------------+
+32 | LOTC | LOTC
+-------------------------------+
+34 | BC | BC
+-------------------------------+
NOTE
Blank registers have been added to the register map to
insure that all normal use registers are at least two
address bits apart. This prevents a single bit
address error from corrupting a SWIFT register.
Most registers in SWIFT are standard read/write registers. Some,
however, do not fall into this class. The other types of registers
SWIFT INTERNAL REGISTERS Page 5-3
3 August 1989
are:
R/W1TC - read/write 1 to clear. The ISTAT Register contains
bits which require that once a status bit has been set, it
can only be cleared by writing a 1 to that bit position. For
example: the microprocessor reads the status register, then
writes the value it read to clear it. Bits set after the
register has been read remain set when the register is
written.
R/O - read only. Applies to a register which contains status
bits only, and therefore cannot be written by the
microprocessor.
R/W - Some of these registers are true read/write registers.
Others are not true read/write in that under certain
conditions they will not read back the value last written to
them. These conditions will be noted in the description of
the register.
SWIFT REGISTER MAP
NAME USAGE CLASS
+---------------+---------------+---------------+
| CSR | Setup | R/W |
+---------------+---------------+---------------+
| ID | Setup | R/W |
+---------------+---------------+---------------+
| TMO | Setup | R/W |
+---------------+---------------+---------------+
| SECSIZ | Setup | R/W |
+---------------+---------------+---------------+
| TLP | DSSI | R/W |
+---------------+---------------+---------------+
| ILP | DSSI | R/W |
+---------------+---------------+---------------+
| DSCTRL | DSSI | R/W,R/O |
+---------------+---------------+---------------+
| ISTAT | DSSI | R/W1TC |
+---------------+---------------+---------------+
| DDB | DIAGNOSTIC | R/W |
+---------------+---------------+---------------+
| DCS | DIAGNOSTIC | R/W |
+---------------+---------------+---------------+
| DICTRL | DIAGNOSTIC | R/W |
+---------------+---------------+---------------+
| OOVSIZ | Setup | R/W |
+---------------+---------------+---------------+
| LOTC | DIAGNOSTIC | R/O |
+---------------+---------------+---------------+
| BC | DIAGNOSTIC | R/O |
+---------------+---------------+---------------+
SWIFT INTERNAL REGISTERS Page 5-4
3 August 1989
NOTE
For the entirety of the document, please keep in mind
that all memory references are made with WORD
addresses. Note that the maximum address size of 18
bits restricts the amount of memory visible to SWIFT
to 128K words.
SWIFT INTERNAL REGISTERS Page 5-5
REGISTER DEFINITIONS 3 August 1989
5.1 REGISTER DEFINITIONS
NOTE
All undefined bits in any non-blank registers (denoted
by "-") will read as zero. Writing to any of these
bits will have no effect.
5.1.1 Control And Setup Registers
These registers are used to set up SWIFT in its operating mode. This
group of registers can be write-protected to prevent accidental access
to them.
5.1.1.1 CSR - Control/Status Register
This register contains control and status information about the
general operation of SWIFT, including various enable bits.
CSR (0) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | - | - | - | - | - |HPM|RST|SPT|EEN| ZF|SLE|IIA| IE|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The fields in the CSR are defined as follows:
o HPM - Set if SWIFT is operating on an arbitrated II bus. In
this mode, SWIFT will handle arbitration. HP_RDY is used as
a BUS_REQ, with SWIFT returning HP_BUSGRANT to indicate that
the external device has control of the bus. When clear
(default on powerup) HP_RDY indicates that the current data
transfer can be terminated and HP_BUSGRANT is not used.
o RST - (ReSeT Command) - Set to reset SWIFT. Once set, this
bit will automatically be cleared by SWIFT when the reset is
completed. The reset takes 200 to 300 nsec to complete.
o SPT - (SPliT) Set if SWIFT is to put the CI overhead in a
separate buffer from the data for data/utility packets. Used
in RF drives along with ZF to format data for
writing-to/reading-from disk.
o EEN - (EDC ENable) Set if SWIFT is to check buffer EDCs for
outbound buffers. SWIFT will always read an EDC, but, if
this bit is cleared , it will not check it. SWIFT will
always generate and write correct EDCs for inbound buffers.
SWIFT INTERNAL REGISTERS Page 5-6
REGISTER DEFINITIONS 3 August 1989
o ZF - (Zero Fill) - Set if SWIFT is to zero-fill the last
buffer of each data packet. For inbound packets, when this
bit is set, if the last word of data of the packet does not
fall in the last word of the last buffer, the remaining words
of the buffer will be written with zeros, and the EDC will be
calculated for each word in the buffer, including the zeros,
then written at the end of the buffer. For inbound packets
without this bit set, the EDC is written immediately after
the last word of data. For outbound packets with this bit
set, if SWIFT gets to the end of the packet before it gets to
the end of a buffer, it will continue to read the rest of the
buffer, then the EDC. If EEN is set, it will then check the
EDC. For outbound packets with this bit cleared, SWIFT will
read the EDC immediately after the last data word. SWIFT
determines that a packet is a Data packet by examining bit 4
of the first byte in the Data Out phase (refer to CI spec).
Note that all odd-byte-length packets will have the high byte
of the last word of data zero-filled regardless of whether
the ZF bit is set or the packet is Data or not.
o SLE - (Selection Enable) - Set if SWIFT is to respond to
selections. Clear (default on reset) otherwise.
o IIA - (Interrupt on Illegal Access) - Set if SWIFT is to
interrupt the processor when an access to a blank or
write-protected register is detected. Clear (default on
reset) otherwise. When clear, SWIFT will never Set IAD in
the ISTAT register. Note that if IE is Clear, SWIFT will not
interrupt the processor, but will update the ISTAT register
appropriately (See ISTAT Register Description).
o IE - (Interrupt Enable) - Set if interrupts are to be
enabled. Clear (the default on reset) otherwise. If clear,
interrupts to the processor are disabled (regardless of the
state of the IIA bit mentioned above), but the ISTAT register
will be updated appropriately (See ISTAT Register
description). If any bit is already set in the ISTAT
register when this bit gets set, SWIFT will issue an
interrupt to the processor.
5.1.1.2 ID - DSSI ID Register
This register contains the three bit ID number of this SWIFT on the
DSSI bus. This value is needed for arbitration and selection. The
value read from this register may not be the last value written, but
will always indicate the DSSI ID SWIFT is currently using.
SWIFT INTERNAL REGISTERS Page 5-7
REGISTER DEFINITIONS 3 August 1989
ID (2) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|P/R| - | - | - | - | - | - | - | - | - | - | - | - |BUS ID<2:0>|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The bits is this register are defined as follows:
o P/R - (Pins/Register) - When Set, indicates that the ID of
SWIFT is the value written to BUS ID in this register. When
cleared (default on reset), the three ID pins of SWIFT
determine the ID that will be used.
o BUS ID - The ID of SWIFT. If P/R is set, these bits read
back what was last written by the processor. When P/R is
cleared, these bits read back the setting of the external ID
pins.
5.1.1.3 TMO - Timeout Register
This register contains the timeout values for both the Initiator and
Target roles. Note that once enabled, the timeout values apply to all
transactions. This register also contains the selection timeout
value.
TMO (4) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | - |SELECTION TIME.|TARGET TIMEOUT |INIT. TIMEOUT |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The bits in this register are defined as follows:
o SELECTION TIMEOUT - the number of 25.6 microsecond intervals
which may elapse from the beginning of selection until SWIFT
aborts the selection. The value written to these bits does
not translate to a simple multiplication of the 25.6
microsecond time factor. Bit 8 represents the highest order
bit, while bits 9,10 and 11 represent the lowest, 3rd highest
and 2nd highest order bits. The value that should be written
to the selection timeout nibble is actually the desired 4 bit
value circularly shifted to the left, such that the highest
order bit ends up in the low bit position and the other three
bits get shifted once to the left. The following table is
provided to show what value should actually be written to
this nibble in order to produce a given 25.6 microsecond
multiplication factor:
SWIFT INTERNAL REGISTERS Page 5-8
REGISTER DEFINITIONS 3 August 1989
Desired
N Selection Timeout Value Written to Nibble
in Hex (N x 25.6 us) in Hex
-------------------------------------------------------------
0 Selection Timeouts Disabled 0
1 25.6 us 2
2 51.2 us 4
3 76.8 us 6
4 102.4 us 8
5 128.0 us A
6 153.6 us C
NOTE
If the selection timeout value written to the
nibble exceeds 153.6 us SWIFT's behavior is
not predictable.
Note that the selection timeout value represents the time at
which SWIFT releases the ID lines. An additional time of
25.6 us will pass before SWIFT releases its DSSI_SEL line as
well. The user should refer to section 9.3.5 of the
specification for more detail. A non-zero value indicates
that the timer is enabled.
o TARGET TIMEOUT - the number of 200 microsecond intervals
which may elapse, starting from the point when SWIFT was
selected until the next observed bus free phase while SWIFT
is in the Target role. Should this timer expire, SWIFT will
immediately disconnect from the DSSI bus. A non-zero value
indicates the timer is enabled.
o INITIATOR TIMEOUT - the number of 200 microsecond intervals
which may elapse, from the last observed bus free phase,
until the next observed bus free phase while SWIFT is in the
Initiator role; or the number of 200 microsecond intervals
which may elapse before SWIFT, acting as a potential
Initiator, detects a bus free phase. Should either of these
conditions occur, SWIFT will assert DSSI bus reset. A
non-zero value indicates the timer is enabled.
5.1.1.4 BUFSIZ - Buffer Size Register
This register contains the maximum number of data words that SWIFT
will put into a receive buffer before appending an EDC, or the maximum
number of data words that SWIFT will read from a transmit buffer
before expecting an EDC. This register allows the user to make a
buffer size other than 256 words. The value written to this register
must be greater than 128 or SWIFT's actions cannot be anticipated.
SWIFT INTERNAL REGISTERS Page 5-9
REGISTER DEFINITIONS 3 August 1989
This register defaults to 0000H on powerup. It is the user's
responsibility to write it with the desired buffer size before
allowing any data transfer.
BUFSIZ (6) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | BUFFER SIZE<12:0> (in words) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
5.1.2 DSSI Registers
This group of four registers is used while the chip is operating. Two
registers are used as pointers; a third is used for enabling SWIFT;
and the fourth is used to report error status.
5.1.2.1 TLP - Target List Pointer
This register contains the address of the buffer in which SWIFT will
attempt to write the next incoming packet. SWIFT will automatically
reload this register with its new value upon completion of the current
transaction. Refer to the DSSI Operation description later in this
document. Note that this address is really a 17-bit word address,
with the lower bit of the address forced to zero . The register
contains the upper sixteen bits of this 17-bit address. SWIFT will
interpret a value of zero as the end of a linked list. This register
can only be written by the microprocessor when the register value is
zero, or the Input Enable bit (in the DSCTRL Register) is zero . All
other attempts to write this register will be ignored. While SWIFT is
updating the TLP or ILP, it will hold off all requests to access any
register until the update is complete. This prevents firmware from
accessing a "stale" pointer. Its default value is 0000H. The user
should read the sections on adding and removing from a linked list for
additional information on how to update the TLP.
TLP (8) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| ADDRESS OF NEXT "INCOMING" BUFFER |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
SWIFT INTERNAL REGISTERS Page 5-10
REGISTER DEFINITIONS 3 August 1989
5.1.2.2 ILP - Initiator List Pointer
This register contains the address of the buffer from which SWIFT will
read the next outgoing packet. SWIFT will automatically reload this
register with its new value upon completion of the current
transaction. Refer to DSSI Operation Description. SWIFT will
interpret a value of zero as the end of a linked list. Note that this
address is really a 17-bit word address, with the lower bit of the
address forced to zero . The register contains the upper sixteen bits
of this 17-bit address. This register can only be written by the
microprocessor when the register value is zero or the Output Enable
bit (in the DSCTRL Register) is zero . All other attempts to write
this register will be ignored. While SWIFT is updating the TLP or
ILP, it will not accept requests to access registers until the update
is complete. This prevents firmware from accessing a "stale" pointer.
Its default value is 0000H. The user should read the sections on
adding and removing from a linked list for additional information on
how to update the ILP.
ILP (14) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| ADDRESS OF NEXT "OUTGOING" BUFFER |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
5.1.2.3 DSCTRL - DSSI Control And Status Register
This register contains information necessary to control and monitor
SWIFT.
DSCTRL (18) -- READ/WRITE, READ ONLY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| IN| MI| - |WP1| - | - |TPZ|IIP|OUT| MO| - |WP2| - | - |IPZ|OIP|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The bits in this register are defined as follows:
o IN - (Input Enable) - when Set, indicates that SWIFT may
receive incoming packets. This bit (and the MI bit) can be
set only by the microprocessor. When cleared, SWIFT will
return a NACK status for every transfer directed toward it.
SWIFT will clear this bit (and interrupt the processor) if
the sync character of a receive buffer is incorrect. This
bit is double buffered; if the microprocessor wishes to
change its value, SWIFT will buffer the value until the next
appropriate interval at which it may be changed (see IIP).
This allows the microprocessor to temporarily disable SWIFT
so that it can manipulate buffers. To set the IN bit, the
SWIFT INTERNAL REGISTERS Page 5-11
REGISTER DEFINITIONS 3 August 1989
microprocessor must write a 1 to both this and the MI bit.
To clear the IN bit, the microprocessor must write a 0 to
both this and the MI bit.
o MI - (Microprocessor's Input Enable) - When read, this bit
reflects the buffered value that will be written to the
'real' Input Enable by SWIFT at the next appropriate time.
For writes, both this bit and the Input Enable bit must match
for any action to be taken. In other words, if the IN and MI
bits are not the same value when written, then neither the IN
or MI bit will be changed. This provides an increased amount
of protection against errors in writing this register.
o WP1 - (Write Protect 1) - This bit, along with WP2, serves to
write protect the non-DSSI registers (i.e. Setup and
Diagnostic registers). When either is Set, any writes
directed at those registers are ignored, and may generate an
interrupt (depending on the state of the IIA bit in the CSR).
When both are cleared, all registers are accessible. Two
bits are used for increased protection against bit errors
while writing this register.
o TPZ - (Target Pointer Zero) - This bit is Set if the Target
pointer is currently zero (0000H). This information can be
used when determining the state of the chip. This bit is
read only. This bit is set when SWIFT has no buffers on the
Inbound List.
o IIP - (Input In Progress) - When set, this bit signifies that
SWIFT is currently receiving an incoming packet. Any attempt
to change the Input Enable bit will be stalled by SWIFT until
this bit becomes clear. This bit is read only. This bit is
set when SWIFT gets selected and is cleared when SWIFT has
completed all linked list operation and disconnected from the
bus.
The IN, MI, TPZ and IIP can be used to determine the state of SWIFT
with respect to inbound traffic. These states are shown below:
IN MI TPZ IIP Description
-- -- --- --- -----------
0 0 0 0 SWIFT has buffers available to it, but needs to be
enabled.
0 0 0 1 SWIFT is currently receiving a packet which it will
NACK because it is not enabled.
0 0 1 0 SWIFT has no buffers available to it and is not
enabled. This is the default on power-up.
0 0 1 1 SWIFT is currently receiving a packet which it will
NACK because it is not enabled and has no buffers.
SWIFT INTERNAL REGISTERS Page 5-12
REGISTER DEFINITIONS 3 August 1989
0 1 0 0 If the OIP bit is set, SWIFT is currently sending OUT
a packet, and will copy the MI bit to the IN bit at
the end of the transfer; see condition 1 1 0 0. If
the OIP bit is not set, condition 0 1 0 0 is not
possible.
0 1 0 1 SWIFT is currently receiving a packet which it will
NACK since it is not enabled. However, at the
completion of the current transfer, SWIFT will become
enabled.
0 1 1 0 If the OIP bit is set, SWIFT is currently sending OUT
a packet, and will copy the MI bit to the IN bit at
the end of the transfer; see condition 1 1 1 0. If
the OIP bit is not set, condition 0 1 1 0 is
impossible.
0 1 1 1 SWIFT is currently receiving a packet, which it will
NACK because it is not enabled and has no buffers
available to it. It will become enabled upon
completion of the transfer, however it will still
have no buffers available to it.
1 0 0 0 If the OIP bit is set, SWIFT is currently sending OUT
a packet, and will copy the MI bit to the IN bit at
the end of the transfer; see condition 0 0 0 0. If
the OIP is not set, condition 1 0 0 0 is impossible.
1 0 0 1 SWIFT is currently receiving a packet, and will
become disabled at the completion of the transfer.
1 0 1 0 If the OIP bit is set, SWIFT is currently sending OUT
a packet, and will copy the MI bit to the IN bit at
the end of the transfer; see condition 0 0 1 0. If
the OIP is not set, condition 1 0 1 0 is impossible.
1 0 1 1 SWIFT is currently receiving a packet, and will
become disabled at the completion of the transfer. It
will also have no buffers available to it.
1 1 0 0 SWIFT has buffers available to it and is enabled, but
is currently not receiving a packet.
1 1 0 1 SWIFT is currently receiving a packet, is enabled and
has buffers available to it.
1 1 1 0 SWIFT is enabled, but has no buffers available to it.
1 1 1 1 SWIFT is enabled and receiving a packet, which it
will NAK because it has no buffers available to it.
SWIFT INTERNAL REGISTERS Page 5-13
REGISTER DEFINITIONS 3 August 1989
o OUT - (Output Enable) - when Set, this bit indicates SWIFT is
enabled to send outbound packets. This bit can be set only
by the microprocessor. See OBC bit in ISTAT Register for a
list of when SWIFT clears this bit. When OUT is cleared,
SWIFT will not attempt to transmit any outgoing packets.
This bit is double buffered. Therefore, if the
microprocessor wishes to change its value, SWIFT will buffer
the value until the next appropriate interval at which it may
be changed (see OIP). This allows the microprocessor to
temporarily disable SWIFT so that it can manipulate buffers.
To set the OUT bit, the microprocessor must write a 1 to both
this and the MO bit. To clear the OUT bit, the
microprocessor must write a 0 to both this and the MO bit.
o MO - (Microprocessor's Output Enable) - when read, this bit
reflects the buffered value that will be written to the
'real' Output Enable by SWIFT. Both this bit and the Output
Enable bit must match for any action to be taken. In other
words, if the OUT and MO bits are not the same value when
written, then neither the OUT or MO bits will be changed.
This allows an increased amount of protection against errors
in writing this register.
o WP2 - (Write Protect 2) - this bit, along with WP1, serves to
write protect the non-DSSI registers (i.e. Setup and
Diagnostic registers). When either is set to 1, any writes
directed at those registers are ignored. When both are
cleared, all registers are accessible. Two bits are used for
increased protection against bit errors while writing this
register.
o IPZ - (Initiator Pointer Zero) - when Set signifies that the
Initiator list pointer is currently zero. This information
can be used when determining the state of SWIFT with respect
to outbound traffic. This bit is read only. This bit is set
when SWIFT has no buffers in its outbound list.
o OIP - (Output In Progress) - when set, this bit signifies
that SWIFT is currently sending an outgoing packet. Any
attempt to change the Output Enable bit will be stalled by
SWIFT until this bit becomes clear. This bit is read only.
This bit is set when SWIFT decides to arbitrate for the bus
and remains set until either SWIFT completes the transfer as
an Initiator, or gets selected as a Target.
The OUT, MO, IPZ and OIP can be used to determine the state of SWIFT
with respect to outbound traffic. These states are shown below:
OUT MO IPZ OIP Description
-- -- --- --- -----------
0 0 0 0 SWIFT has buffers available to it, but needs to be
enabled.
SWIFT INTERNAL REGISTERS Page 5-14
REGISTER DEFINITIONS 3 August 1989
0 0 0 1 Impossible condition.
0 0 1 0 SWIFT has no buffers available to it and is not
enabled. This is the default on power-up.
0 0 1 1 Impossible condition.
0 1 0 0 If the IIP bit is set, SWIFT is currently receiving a
packet, and will copy the MO bit to the OUT bit at
the end of the transfer; see condition 1 1 0 0. If
the IIP is not set, condition 0 1 0 0 is impossible.
0 1 0 1 SWIFT is currently receiving a packet, which it will
NAK because it is not enabled. It will become
enabled, however, at the end of the transfer.
0 1 1 0 If the IIP bit is set, SWIFT is currently receiving a
packet, and will copy the MO bit to the OUT bit at
the end of the transfer; see condition 1 1 1 0. If
the IIP is not set, condition 0 1 1 0 is impossible.
0 1 1 1 Impossible condition.
1 0 0 0 If the IIP bit is set, SWIFT is currently receiving a
packet, and will copy the MO bit to the OUT bit at
the end of the transfer; see condition 0 0 0 0. If
the IIP is not set, condition 1 0 0 0 is impossible.
1 0 0 1 SWIFT is currently sending data, and will become
disabled at the completion of the transfer.
1 0 1 0 If the IIP bit is set, SWIFT is currently receiving a
packet, and will copy the MO bit to the OUT bit at
the end of the transfer; see condition 0 0 1 0. If
the IIP is not set, condition 1 0 1 0 is impossible.
1 0 1 1 Impossible condition.
1 1 0 0 SWIFT has buffers available to it and is enabled, but
is currently not sending a packet.
1 1 0 1 SWIFT is currently sending a packet.
1 1 1 0 SWIFT is enabled, but has no buffers available to it.
1 1 1 1 Impossible condition.
5.1.2.4 OOVSIZ<4:0> - Other OVerhead SIZe
The OOVSIZ register is used to allow SWIFT to handle CI data packet
overheads of other than 9 words. This was implemented because while
SWIFT INTERNAL REGISTERS Page 5-15
REGISTER DEFINITIONS 3 August 1989
SWIFT was being designed, there was much talk about adding some new CI
packet types which would have overhead sizes larger than 9 words, but
at the time there was no agreement about how large the new overheads
would be. The new packets were to be differentiated from the old
packets by bit 7 of the CI command word being set. When the packet is
DATA/UTILITY, SPT is set, and bit 7 of the CI command word is set,
SWIFT will use the value in OOVSIZ rather than 9 words as the length
of the first buffer of the the packet.
OOVSIZ (6) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | - | - | - | - | - | - | - | - |OOVSIZE<4:0>(words)|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
5.1.2.5 ISTAT - Interrupt Status Register
This register contains interrupt status. All bits are W1TC. The
value of IE in the DSCTRL register has no effect on whether these bits
are set, only on whether they generate an interrupt to the
microprocessor.
ISTAT (20) -- READ/WRITE 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - |BFB|IDN|IER|INB|ODN|RST|RT3|RTO|EPE|IPE|IAD|IBC|OBC|SNF|LDN|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
These bits are defined as follows:
o BFB - (Bad First Buffer) - this bit is Set if SWIFT
encounters a bad sync character in the first buffer of the
packet. In this case SWIFT will not write any status to the
packet's status word, as the buffer is probably invalid.
o IDN - (Input DoNe) - this bit is Set when SWIFT, acting as a
Target, has SUCCESSFULLY received a packet.
o IER - (Input ERror) - this bit is Set when SWIFT, acting as a
Target, encounters any error while receiving a packet.
o INB - (INbound Buffer error) - this bit is Set if SWIFT,
acting as a Target, does not have enough buffers to complete
the packet.
o ODN - (Output DoNe) - this bit is Set when SWIFT, acting as
an Initiator, has SUCCESSFULLY completed the transfer of a
packet.
SWIFT INTERNAL REGISTERS Page 5-16
REGISTER DEFINITIONS 3 August 1989
o RST - (ReSeT) - this bit is Set when SWIFT detects that a
DSSI reset occurred - regardless of its current role on the
bus.
o RT3 - (Third party ReseT) - this bit is Set if SWIFT detected
a reset on the DSSI bus, while it was idle - acting as
neither an Initiator nor a Target.
o RTO - (Originator ReseT) - this bit is Set if SWIFT generated
a reset on the DSSI bus.
o EPE - (External Parity Error) - this bit is Set if SWIFT,
acting as a Target, encounters a parity error on the DSSI
bus.
o IPE - (Internal Parity Error) - this bit is Set if SWIFT,
acting as Target, encounters a parity error AFTER the data
has entered SWIFT, i.e., the data was corrupted within SWIFT.
This bit will not be set if the error is encountered on the
DSSI bus.
o IAD - (Illegal Access Detected) - this bit is Set if the IIA
bit in the CSR register is set and the processor attempts to
access an unassigned (blank) register or the processor
attempts to write a write-protected register. This bit is
never set when the IIA bit is clear. If, at the time the IIA
bit in the DSCTRL register is Cleared, this bit is Set, it
will remain Set until Cleared by the processor.
o IBC - (IN Bit Cleared) - this bit is Set if, as a Target, an
incorrect sync pattern was found in an inbound buffer.
o OBC - (OUT Bit Cleared) - this bit is Set if :
1. As an Initiator, SWIFT received RST while transmitting
data to another node.
2. As an Initiator, SWIFT's DSSI timer reached the Initiator
timeout value while transmitting data.
3. As an Initiator, SWIFT's DSSI timer reached the selection
timeout value while selecting a Target.
4. As an Initiator, the attached Target disconnects
unexpectedly.
5. As an Initiator, a NACK status was returned on an
outgoing packet.
6. As an Initiator, an incorrect sync pattern was found in
an outbound buffer.
SWIFT INTERNAL REGISTERS Page 5-17
REGISTER DEFINITIONS 3 August 1989
7. As an Initiator, an unexpected DSSI bus phase was
encountered.
8. As an Initiator, an EDC error was detected upon reading
the packet command bytes or data from memory.
o SNF - (Sync Not Found) - this bit is Set if SWIFT encountered
a sync character which was not AAAA5555H. If this condition
occurs, SWIFT will disable the appropriate enable (IN or OUT)
in the DSCTRL Register and stop transfers in that direction.
This bit is not set if the bad sync was found in the first
buffer.
o LDN - (List Done) - this bit is Set if SWIFT has completed a
packet, whether successfully or not.
5.1.3 Diagnostic And Test Registers
This group of registers is used to test SWIFT. Two of the registers
are used to observe and control the DSSI bus while doing diagnostics.
The remaining register is used to enable the various test modes of the
chip. This group of registers is to be used only for initialization,
test, and diagnostic purposes. They should never be used while in
normal operation. They can be write-protected to prevent accidental
access to them.
5.1.3.1 DDB - DSSI Data Bus
The DDB register is used in diagnostic mode (see DICTRL description)
in conjunction with a loop back connector to test the DSSI port. It
is also used in diagnostic internal loopback mode to effectively act
like the DSSI bus. The fields in this register directly reflect the
DSSI data bus ASSERTED HIGH. This register should NOT be used during
normal operations. It should be noted that care must be taken to test
this portion of the chip without any disturbance to the DSSI bus (See
TEST STRATEGY).
DDB (22) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - - - - - - - |PTY| SP DATA <7:0> |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
SWIFT INTERNAL REGISTERS Page 5-18
REGISTER DEFINITIONS 3 August 1989
5.1.3.2 DCS - DSSI Control Signals
This register is used in diagnostic mode (see DICTRL description) in
conjunction with a loop back connector to test the DSSI port or to
effectively act as the DSSI bus in internal loopback mode. The bits
in this register directly reflect the DSSI control lines ASSERTED
HIGH. It should be noted that data written to this register may
differ from that read back since only certain bits are driven while in
the Target or Initiator mode. (See TEST STRATEGY)
DCS (24) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | - | - | - | - | - | - |BSY|SEL|RST|ACK|REQ|C/D|I/O|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
5.1.3.3 DICTRL - Diagnostic Control Register
This register contains the various control bits used in diagnostic
mode. Note that the signals in this register behave somewhat
differently than the control signals on the DSSI Bus (See TEST
STRATEGY).
DICTRL (26) -- READ/WRITE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | - | - | - | - | - | - | - |SRD|TST|DOE|COE|LPB|PRE|DIA|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The bits is this register are defined as follows:
o SRD - (Status Register Diagnostics) - Set to enable the ISTAT
Register to be written as a normal register for diagnostic
purposes. When clear, the ISTAT Register remains
write-1-to-clear.
o TST - (Test Bit) - Set, only for fault-grading purposes.
This bit will cause the DSSI timeout counters to increment
more quickly than usual.
o DOE - (Data Output Enable) - Set to enable the DSSI data
drivers. This should be used only in conjunction with the
external loopback mode to test the chip's drivers. Clear
(default on reset) otherwise.
o COE - (Control Output Enable) - Set to enable the DSSI
control signal drivers. This should be used only in
conjunction with the external loopback mode to test the
chip's drivers. Clear (default on reset) otherwise. If
SWIFT INTERNAL REGISTERS Page 5-19
REGISTER DEFINITIONS 3 August 1989
software attempts to set both the DOE and COE bit, this bit
will remain cleared and DOE will be set.
o LPB - (Internal Loopback) - Set if the values written to the
diagnostic registers are to be looped back into the chip.
This will enable the microprocessor to insert test vectors
into the chip during power-up diagnostics if desired. Note
that the DIA bit must be deasserted for this test to be
meaningful. Clear (default on reset) otherwise. Refer to
TEST STRATEGY.
o PRE - (Port Enable) - Set to enable the DSSI drivers. After
a reset, SWIFT will be disconnected from the bus (this bit
will be zero). The primary purpose of this bit is to allow
chip diagnostics to run without affecting the rest of the
DSSI bus. Note that this bit MUST be set for normal
operation of SWIFT or for the external loopback test mode of
SWIFT.
o DIA - (Diagnostic Mode) - When this bit is asserted, SWIFT is
in external loop-back mode. In this mode, the diagnostic
registers directly control the DSSI data and control lines,
as well as the bus steering signals. After a RESET
condition, this bit is zero . Refer to TEST STRATEGY.
SWIFT INTERNAL REGISTERS Page 5-20
REGISTER INITIALIZATION VALUES 3 August 1989
5.2 REGISTER INITIALIZATION VALUES
The following table is a summary of the values which should appear in
SWIFT registers following a hard or soft reset. Those marked by "X"
indicate that the bit is indeterminate after reset.
NAME BIT VALUES
---- --- ------
CSR 0000 0000 0000 0000
ID 0000 0000 0000 0XXX
TMO 0000 0000 0000 0000
BUFSIZ 0000 0000 0000 0000
TLP 0000 0000 0000 0000
ILP 0000 0000 0000 0000
DSCTRL 0000 0010 0000 0010
ISTAT 0000 0000 0000 0000
DDB 0000 000X XXXX XXXX
DCS 0000 0000 0XXX XXXX
DICTRL 0000 0000 0000 0000
OOVSIZ 0000 0000 0000 0000
CHAPTER 6
DSSI OPERATION
SWIFT is specifically intended to be used with Digital's Storage
System Interconnect (DSSI). SWIFT provides many of the bus functions
required by the data link layer using a minimal number of
microprocessor interrupts. SWIFT controls all DSSI bus protocol,
meeting the specifications outlined in Digital's Storage System
Interconnect, Addendum to DEC STD 161. It controls the bus
arbitration, selection, command, data, and status phases of a
transfer. It implements a "fair" arbitration scheme and provides for
selection, initiator, and target timeouts. The following is taken
from the aforementioned specification, and summarizes the DSSI Bus
Sequences:
DSSI OPERATION Page 6-2
3 August 1989
+---------------+
| |
| Bus Free |<------+
| | |
+---------------+ |
| |
V |
+---------------+ |
| | (1) |
| Arbitration |-------+
| | |
+---------------+ |
| |
V |
+---------------+ |
| | (2) |
| Selection |-------+
| | |
+---------------+ |
| |
V |
+---------------+ |
(4) | | (3) |
+-------| Command Out |-------+
| | | |
| +---------------+ |
| | |
| V |
| +---------------+ |
| | | (5) |
| | Data Out |-------+
| | | |
| +---------------+ |
| | |
| V |
| +---------------+ |
| | | (6) |
+------>| Status In |-------+
| |
+---------------+
The normal path follows vertically downward. Exception paths are
listed below:
1. The initiator arbitrates and loses.
2. The target failed to respond or responded with an unexpected
bus phase.
3. The operation was timed out or the target responded with
unexpected phase.
DSSI OPERATION Page 6-3
3 August 1989
4. The target detected a parity error or information mismatch in
the command, or the target did not have any buffer space
available.
5. The operation was timed out or the target responded with an
unexpected phase.
6. Entire transfer phase sequence occurred successfully - this
is the normal case.
CHAPTER 7
SWIFT OPERATION - USER INTERFACE
SWIFT is specifically intended to be used with Digital's Small Storage
Interconnect. The user MAY define a few aspects of DSSI bus
operation, and MUST format the send and receive buffers that SWIFT
will operate on. The user must also set up the internal registers,
such as the TLP, ILP, BUFSIZ and CSR registers, such that they
accurately reflect the buffers that have been prepared. This chapter
is intended to show the user the requirements and options of SWIFT.
7.1 DSSI USER SELECTABLE OPTIONS
SWIFT will handle all DSSI protocol, as described in chapter 6. The
USER, however, controls the following aspects of a DSSI bus transfer:
1. Whether or not SWIFT will respond to being selected by an
Initiator. If the SLE bit is set, SWIFT will assert
DSSI_BSY_L in response to selection by a potential Initiator
and become a Target; if not set, SWIFT will do nothing in
response to being selected.
2. When and if SWIFT checks for target, initiator, or
selection timeouts on the DSSI bus is determined by the value
written to the TMO register.
3. Whether or not SWIFT will arbitrate for the bus as an
Initiator is determined by the OUT bit in the DSCTRL register
and the contents of the ILP register. It is by providing a
nonzero value in the ILP register and setting the OUT and MO
bits in the DSCTRL register that the user enables SWIFT to
arbitrate for the DSSI bus and potentially become an
Initiator.
4. Whether or not SWIFT will attempt to receive a packet
when selected as a Target is determined by the the IN bit in
the DSCTRL register and the contents of the TLP register. It
is by providing a nonzero value in the TLP register, and
setting the IN and MI bits in the DSCTRL register, that the
user allows SWIFT to accept a packet from an Initiator. If
either the TLP register is zero, or the IN bit is clear,
SWIFT OPERATION - USER INTERFACE Page 7-2
DSSI USER SELECTABLE OPTIONS 3 August 1989
SWIFT will respond to selection by a potential initiator, but
will immediately jump to the Status In phase and NACK the
packet. It will continue to do this until the user rectifies
the situation.
7.2 FORMATTING PACKETS AND BUFFERS
7.2.1 Overview
NOTE
In this document, packets and buffers do NOT refer to
the same thing. Packets are the vehicle for
transferring data on the DSSI bus. The format of
packets is determined by the CI Specification (DEC
Std. 161) and the DSSI Addendum to the CI
Specification. Some of the content of a packet is
determined by the CI PORT spec. Buffers are
structures in memory where data is stored before and
after being transferred on the DSSI bus. Buffers can
be thought of as holding packets. All buffers have
the same general format, but there are some specifics
which are dependent on the content of the packet the
buffers are holding, and on the values of several
registers internal to SWIFT. SWIFT does the
translation between packets on the DSSI bus and
buffers in memory. The relationship between packets
and buffers is not one to one; several buffers may
translate into one packet, but one buffer can
translate into no more than one packet.
SWIFT keeps its buffers in two linked lists. One list holds empty
buffers into which SWIFT will put inbound packets. The other list
holds nonempty buffers from which SWIFT will create and send outbound
packets. Each list may hold one or more packets' worth of buffers.
NOTE
In this document, INBOUND PACKET refers to a packet
which SWIFT is receiving on the DSSI bus when acting
as a Target. OUTBOUND PACKET refers to a packet which
SWIFT is sending on the DSSI bus When acting as an
Initiator.
For SWIFT to receive a packet on the DSSI bus, the microprocessor must
first set up the chip. It must then provide SWIFT with empty buffers.
Once the microprocessor has created and linked together the empty
buffers, it writes the address of the first buffer into SWIFT's TLP
register and sets MI and IN. SWIFT will then put any inbound packet
into the buffer(s) provided by the microprocessor.
SWIFT OPERATION - USER INTERFACE Page 7-3
FORMATTING PACKETS AND BUFFERS 3 August 1989
For SWIFT to send a packet across the DSSI bus, the packet must
first be put into a buffer or buffers. This is done by the
microprocessor according to the same rules SWIFT uses to put inbound
packets into buffers. Once the buffers are ready, the microprocessor
loads the address of the first buffer of the packet into the ILP
register and sets the MO and OUT bits in the DSCTRL. Conceptually,
SWIFT will then read the buffers provided by the microprocessor,
create a packet out of them, and attempt to send it on the DSSI bus.
Actually, all three operations happen concurrently.
7.2.2 General Buffer Format
All buffers used by SWIFT have the same structure. This is to
simplify buffer management and buffer handling by SWIFT. All buffers
must begin on longword boundaries, i.e. the two least significant
address bits must be zero.
The general format of a SWIFT buffer is:
byte General Buffer
address
+-----------------------------------------------+
base+0 | Thread word |
+-----------------------------------------------+
base+2 | Status/Sync word 1 |
+-----------------------------------------------+
base+4 | Sync word 2 |
+-----------------------------------------------+
base+6 | Command word |
+-----------------------------------------------+
base+8 | Command Bytes (6 bytes, 3 words) |
+-----------------------------------------------+
base+14 | Command Bytes EDC |
+-----------------------------------------------+
base+16 | Data (n bytes) |
+-----------------------------------------------+
base+16+n| Data EDC |
+-----------------------------------------------+
The elements of the buffer are defined as follows:
o Thread Word - The Thread Word is a pointer to the next buffer
in this list. A zero in this location indicates this is the
end of the linked list, i.e. the last buffer in the list.
The Thread Word will be the byte address, shifted to the
right by two places, of the beginning of the next buffer in
the list - i.e. the longword address of the next buffer.
o Status/Sync Word 1 - SWIFT expects this word to read AAAAH
before it uses the buffer. After a transfer is completed,
either inbound or outbound, SWIFT will write the transfer
SWIFT OPERATION - USER INTERFACE Page 7-4
FORMATTING PACKETS AND BUFFERS 3 August 1989
status to the Status/Sync Word 1 of the first buffer of the
packet. SWIFT will not change the Status/Sync Word 1 of any
non-first buffers of the packet.
o Sync Word 2 - SWIFT expects this word to read 5555H before it
uses the buffer. Sync Word 1 and Sync Word 2 together form
the Sync Character. The Sync Character is used to verify
buffers. See the Data Integrity section for details. If the
Sync Character is incorrect in either an inbound or outbound
buffer, SWIFT shall assume the buffer is bad (see the
Initiator or Target operation chapters for information on how
SWIFT handles these conditions). SWIFT never writes to Sync
Word 2.
o Command Word - The Command Word contains instructions to
SWIFT regarding the transfer. This word is valid only in the
first buffer of a packet. In subsequent buffers, it is
ignored by SWIFT. SWIFT never writes to the Command Word
This bits in this word are:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|IOC| - | - | - | - | - | - | - | - | - | - | - | - | DEST ID |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The bit fields in this memory word represent the following:
o IOC - (Interrupt On Completion) - When IE is Set in the
DSCTRL register and this bit is set in the first buffer
of a packet, SWIFT will assert SYSINTERRUPT upon
completion (successful or not) of the packet. When this
bit is Clear, SWIFT will not assert SYSINTERRUPT when
done with a packet unless an error has occurred. When IE
is Clear, SWIFT will not assert SYSINTERRUPT when done
with a packet.
o DEST ID - For outbound buffers, the ID of the Target to
be selected. Not used in inbound buffers.
o Command Bytes - The Command Bytes are the 6 byte sequence
sent in COMMAND OUT phase on the DSSI bus by the Initiator.
The Command Bytes section of the buffer is used by SWIFT only
in the first buffer of the packet. In subsequent buffers,
SWIFT ignores the Command Bytes section. For outbound
packets, SWIFT expects the microprocessor to have filled this
section with the data defined in the DSSI spec. For inbound
packets, SWIFT will put the data sent in the COMMAND OUT
phase here.
The format of the Command Bytes is:
SWIFT OPERATION - USER INTERFACE Page 7-5
FORMATTING PACKETS AND BUFFERS 3 August 1989
Command Bytes
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| REQ/ACK Offset| Reserved | Command Op. Code |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| Source Port | Destination Port |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 0 | 0 | 0 | Frame Length |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
1. REQ/ACK Offset - The number in this field partially
determines what offset is to be used during the DATA
PHASE. For outbound packets, the microprocessor should
set this number to 7, since SWIFT does not check the
number in this field, but instead always uses 7 for
outbound transfers. If the microprocessor puts a 3 in
this field, no damage will be done, but the transfer
could potentially be slower. The REQ/ACK offset actually
used in a transfer is controlled by the Target, and is
calculated by the Target to be the minimum of the the
value it receives in this field and the highest offset it
can handle. For an inbound packet, this number may read
3, 7, or 15. If the number is 3, SWIFT used a REQ/ACK
offset of 3. If the number is 7 or 15, SWIFT used a
REQ/ACK offset of 7.
2. Command Op. Code - The number in this field is defined
by the DSSI Spec, Appendix A, to be E0H. It is checked
by SWIFT in inbound packets, but is not checked in
outbound packets.
3. Source Port - The number in this field represents the
port address of the source of the packet. For inbound
packets, this number will indicate the address of the
other node. For outbound packets, this number should be
the port address of this node. Note that the the three
low order bits of the port address are the DSSI address;
SWIFT depends on this when checking inbound packets. For
inbound packets, SWIFT compares the three low order bits
of this number with the DSSI address of the node which
selected it, as indicated in the Selection phase. SWIFT
does not check the five high order bits. Note that for
outbound packets, this is NOT where SWIFT gets its
information about which node to select; that is extracted
from the Command Word. No checking is done for outbound
transfers.
4. Destination Port - The number in this field represents
the port address of the destination of the packet. For
outbound packets, this number should be the port address
of the other node. For inbound packets, this number
SWIFT OPERATION - USER INTERFACE Page 7-6
FORMATTING PACKETS AND BUFFERS 3 August 1989
should indicate port address of this node. For inbound
packets, SWIFT compares the three low order bits of this
number with its DSSI address as indicated in the ID
register. SWIFT does not check the five high order bits.
No checking is done for outbound transfers.
5. Frame Length - This number is the length in bytes of the
data section of the packet. According to Appendix A in
the DSSI Spec, the maximum value for the Frame Length is
4500. SWIFT does not explicitly check that this
restriction is met. This word is where SWIFT gets its
information about the length of the packet. Note that
this number does not have to be an integral multiple of
the byte length of a buffer's data section.
o Command Bytes EDC - The Command Bytes EDC is the error
detection code for the command bytes. For outbound packets,
this word is always read by SWIFT but is checked only if EEN
is set. For inbound packets, SWIFT always generates and
writes this word. This word is valid only in the first
buffer of a packet. Note that this is not the same as the
Command Bytes Checksum which is sent over the DSSI bus.
o Data Block - The Data Block holds the data of the DSSI
packet. The packet data may be split up into several buffers
(see below). SWIFT has several Data Block formats. The
format used in a particular buffer is dependent on several
factors (see below). The working maximum size of a Data
Block is the value in the BUFSIZ register. The maximum
possible size of a Data Block is 4095 words, although the
largest practical value is 2225 words, since the maximum DSSI
packet length is 4500 bytes.
o Data Block EDC - The Data Block EDC holds the EDC of the Data
Block if the Data Block is completely full. If it is not
full, the EDC will be immediately following the last word of
data (see below). For outbound packets, this word is always
read by SWIFT but is checked only if EEN is set. For inbound
packets, SWIFT always generates and writes this word.
7.2.3 Why SWIFT Has Multiple Data Block Formats
SWIFT is intended to be used as the DSSI interface chip for both hosts
and disk drives. Disk drives work on units of data called sectors,
and each sector typically holds 512 bytes of data. In a disk drive,
by setting the BUFSIZ to be 256 (words), SWIFT will expect buffers to
be exactly the size of the drive's sectors. This is very useful for
preformatting data so the drive's microprocessor does not have to
format the data and generate an EDC for every sector. Conversely,
hosts typically use data in monolithic chunks. By setting the BUFSIZ
SWIFT OPERATION - USER INTERFACE Page 7-7
FORMATTING PACKETS AND BUFFERS 3 August 1989
to be 2225 (the current maximum length of a DSSI packet, in words),
SWIFT will expect buffers large enough to hold entire DSSI packets.
These two different operating environments are the primary reason why
SWIFT has multiple Data Block formats.
7.2.3.1 Types Of DSSI Packets
There are two distinct types of packets on the DSSI bus: Data and
Message. Data packets are distinguished from Message packets by the
first word of data in a packet. SWIFT checks this word in every
packet to determine if the packet is Data or Message. Message packets
are essentially overhead; they are used for requesting and
acknowledging Data packets, among other things, but not for
transferring data. From a disk drive's point of view, Message packets
are never written on or read from a disk, they are communications
between the disk's microprocessor and the host. Data packets, as the
name implies, are used to transfer data between the devices on the
bus. There is, however, some non-data information contained at the
beginning of each Data packet. This non-data (CI Overhead) is control
overhead imposed by the CI Port layer, and is currently fixed to be 18
bytes long.
NOTE
In this section, the term real data will be used to
refer to that portion of a Data packet which is not CI
Overhead information.
To a disk drive, the CI Overhead is solely for the use of the
microprocessor, and the rest of the Data packet is the information to
be written to or read from the disk. When a SWIFT in a disk drive is
converting a Data packet into buffers, it separates the CI Overhead
from the real data so the real data is preformatted properly for
writing to disk. SWIFT expects outbound Data packet buffers to be
split up in the same fashion. The host treats the Data packet as one
block of data, so when SWIFT is operating in a host, it does not
separate the real data from the CI Overhead in a Data packet.
7.2.3.2 SPT Bit
The SPT bit in the CSR determines whether SWIFT splits up Data packets
or not. When the SPT bit is set , SWIFT will automatically place the
CI Overhead into a separate buffer from the real data, or expect the
CI Overhead to be in a separate buffer from the real data. The real
data, then, will begin in the second buffer of the packet. This
allows the micoprocessor to transfer the data sections of buffers
directly to/from the disk without manipulating the data. SPT does not
affect the way Message packets are handled.
SWIFT OPERATION - USER INTERFACE Page 7-8
FORMATTING PACKETS AND BUFFERS 3 August 1989
7.2.3.3 Where To Find The EDC For The Data Block
Except for one case (see below), the EDC for a Data Block is always
immediately after the last word of data in each buffer. When a
buffer's Data Block is completely full, the EDC for the Data Block
will be in the Data Block EDC location. However, when the Data Block
is not full, the EDC will be within the Data Block. This means that
when SPT is set, the first buffer of a Data Packet, which holds only
the 9 word CI Overhead, has the EDC for its Data Block as the tenth
word of the Data Block. Similarly, EDCs for Message packets which are
shorter than the size of a buffer are within the Data Block. If a
Message packet is longer than a single buffer but shorter than two
buffers, the EDC of the first buffer is in the Data Block EDC slot,
and the EDC of the second buffer is after the last word of data.
EDC's for the buffers holding the real data of a Data packet work in a
similar way. Any real data buffer which is full has its EDC in the
Data Block EDC slot. However, the EDC for the last buffer in a Data
packet may be either directly after the last word of data or in the
Data Block EDC slot, even if the last buffer is not completely full.
7.2.3.4 Zero-Filling
As mentioned previously, disk drives work on sectors of data which are
256 data words long. A sector is the smallest unit of data which can
be read from or written to a disk. Each sector also has an EDC to
protect the sector's data. The EDC is always after the 256th word of
data and is always one word long. The EDC is generated by SWIFT
before data is written to the disk, and it is checked by SWIFT when
the buffer containing the data from the sector is sent out on the DSSI
bus.
DSSI and the higher level protocols, such as the CI PORT and
MSCP, allow transfers of real data with lengths which are non-integral
multiples of 512 bytes. This can create problems with generating and
checking EDC's.
Example
A host may ask a disk for 42 real bytes of data.
Since the disk must read an entire sector, the drive's
processor will give SWIFT a Data Packet consisting of
two buffers: the first containing the CI Overhead and
its EDC, and the second containing a whole sector's
worth of data and its EDC. The processor will have
set the Frame Length field to be 60 (18+42). As SWIFT
is sending the data, it is keeping track of how many
bytes it has sent. After it has sent the 60th byte,
it would want to check the EDC of the second buffer to
make sure the data in it was valid. The problem is
that the buffer's EDC covers all 256 words of the
buffer. The solution is for SWIFT to read the rest of
the buffer without sending the extra data to the host,
SWIFT OPERATION - USER INTERFACE Page 7-9
FORMATTING PACKETS AND BUFFERS 3 August 1989
then check the buffer's EDC at the end. Similarly, if
the host asks the disk to write 42 real bytes of data,
SWIFT will receive all the bytes, then will have to do
something to fill up the rest of the buffer so it can
put the EDC in the Data Block EDC location. In this
case, SWIFT will write zeros to the rest of the Data
Block, using those zeros in its EDC calculations, then
write the EDC for all 256 words in the buffer (21 real
data words + 235 zero words).
These operations are called zero-filling, and are enabled by setting
the ZF bit in the CSR. Zero-filling can occur only on the last buffer
of a Data packet when ZF is set. If SPT and ZF are set , zero-filling
will occur in the last buffer when a Data packet has a real data
length that is not an integral multiple of the buffer Data Block
length. If ZF is set and SPT is clear, zero-filling will occur in the
last buffer of a Data packet when the packet's Frame Length is not an
integral multiple of the Data Block length. Note that typically SPT
and ZF are either both set or both clear.
7.2.3.5 Other Overhead Size (OOVSIZ)
At the time SWIFT was being designed, there was discussion about an
ECO to the CI PORT spec which would create a new set of Data packets
with CI Overheads longer than 18 bytes. However, there was no
agreement on how large the new CI Overheads would be. The method for
distinguishing the old type of data packet from the new type was
defined, though, so SWIFT knows how to distinguish between Data
packets with an 18 byte CI overhead and Data packets with the "other
overhead size". When the other overhead size is defined, SWIFT will
be able to split up the new type of data packets through the use of
the OOVSIZ register. This register will have to be written by the
microprocessor with the length, in words, of the other overhead size.
If the ECO never goes through, this register can be ignored. If the
ECO creates an overhead with an odd byte length overhead or more than
one other overhead length, SWIFT will not be able to split up those
types of Data packets.
7.2.4 Adding To A Linked List
The following enumerates the steps required to dynamically add new
buffers to the TLP and ILP lists.
1. Fill in the new buffer command block and insure that the two
sync words are correct. The thread word of the new buffer
must be zero or point to another valid buffer.
2. Update the thread word of the last buffer on the list to
point to the first new buffer to be added.
SWIFT OPERATION - USER INTERFACE Page 7-10
FORMATTING PACKETS AND BUFFERS 3 August 1989
3. Read the xLP. Is it 0? No, then don't update the xLP - you
are done. Yes, continue with step 4.
4. Is the first sync character of the last buffer still there?
Yes, this indicates that status has not been written to that
buffer yet and you should continue with step 5. No, then
don't update the xLP - you are done.
5. If you are adding to the TLP list turn off the IN and MO bits
in the DSCTRL register. If you are adding to the ILP list
turn off the OUT and MO bits in the DSCTRL register.
6. Write the xLP with the new thread word, pointing to the new
buffer.
7. Read the xLP. If the xLP is not the value you just wrote, go
back to step 6 and repeat. If the xLP is the value you just
wrote, go to step 8.
8. If you added to the TLP list, turn the IN bit in the DSCTRL
register back on by setting IN and MI in the DSCTRL register.
If you added to the ILP list, turn the OUT bit in the DSCTRL
register back on by setting OUT and MO in the DSCTRL
register. You are done.
NOTE
When specifically changing the IN and MI bits in the
DSCTRL register, write the OUT and MO bits with
complementary values to insure that they are not
changed as well. When specifically changing the OUT
and MO bits in the DSCTRL register, write the IN and
MI bits with complementary values to insure that they
are not changed as well. The IN and MI pair and the
OUT and MO pair can only be changed by the
microprocessor if the pair is written with the same
value at the same time.
7.2.5 Removing From A Linked List
The following enumerates the steps required to remove unused buffers
from the TLP and ILP lists.
1. Clear the appropriate Enable (IN or OUT) bit in the DSCTRL
register.
2. Test this bit and the OIP/IIP bits until they both read zero.
This will insure that SWIFT was not arbitrating and winning
the bus, while the microprocessor was disabling it as an
Initiator.
SWIFT OPERATION - USER INTERFACE Page 7-11
FORMATTING PACKETS AND BUFFERS 3 August 1989
3. Once both bits are cleared, any buffer manipulation can be
done, since the list will remain static.
7.3 SWIFT TO USER - CONTROL/STATUS INFORMATION
The user formats and prepares the outgoing packet or receive buffers,
loads the ILP or TLP with the starting address of a buffer, and sets
the OUT or IN bit in the DSCTRL register to start or enable the
transfer. SWIFT, in turn, completes the transfer, alerts the user
when the transfer is complete, and returns to the user status
information about the transfer.
7.3.1 Indicating That The Transfer Is Complete
SWIFT alerts the user that a transfer is complete via the SYSINTERRUPT
line. Interrupts are enabled by the user via the IEN bit in the CSR
register.
7.3.2 Providing Transfer Status - Packet Status Word
SWIFT provides status information on a transfer via the ISTAT
register, and the status word of a packet. Packet status is written
to the 2nd word of the first buffer of a packet, upon completion of
the packet transfer; it is written over what was previously used as
the first sync character. The following is a description of the bits
in the status word of the packet:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|DNE| BUFFER COUNT<5:0> |NEB|MEM|NRP|NAK|BPH|DSA|PAR|XSM|SNF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
- DNE - DoNE bit, is set when a packet has been completed,
whether successfully or not, or when the microprocessor puts
the first sync character in a buffer. It should be noted
that as this bit is set in the sync character, it should NOT
be used to determine if the packet has been completed. A
packet has been completed when its sync character has been
overwritten by the status word; thus, it will no longer be
AAAAH, as this is an impossible combination for a packet
status word. The DNE bit, by itself, is therefore useless to
the microprocessor. Only if it is 0, does it indicate a
problem, as no microprocessor-prepared buffer should ever
have a 0 in the DNE bit location. A 0 in this bit location
could indicate many problems: the Sync/Status location had
been written over with some kind of erroneous data after the
SWIFT OPERATION - USER INTERFACE Page 7-12
SWIFT TO USER - CONTROL/STATUS INFORMATION 3 August 1989
buffer had been checked, the buffer was never validated in
the first place, the microprocessor wrote the wrong Sync
Character (or 5555H) to it, etc.
- BUFFER COUNT<5:0> This value should be interpreted
differently for inbound and outbound packets.
1. For inbound packets the following rules apply. If the
packet was successfully received, this value represents
the number of buffers in the received packet. If the
packet was unsuccessfully received, this bit represents
the number of buffers that were checked and filled, up to
and including the time the error occurred. It should be
noted that a Target performs a "burn-one-buffer" ending
for all errors other than a SNF and BFB error. Thus, if
a Target determines that the packet is bad due to such
things as bad parity, a Target timeout, a RST on the DSSI
bus, not enough buffers etc., it will "burn-one-buffer".
This means that it will NAK the status of the first
buffer of the packet by writing the appropriate status
word, and update the TLP with the address of the second
buffer of the packet. This allows the Target to use one
buffer instead of several. THERE IS ONE EXCEPTION to
this, and that is when a bad sync character is found in
either a first buffer (BFB) or non-first buffer (SNF).
In the BFB case, the Target automatically clears the IN
bit in the DSCTRL register and leaves the TLP pointing to
the first buffer of the packet; status IS NOT written to
that buffer, thus the buffer count bits don't mean
anything. In the SNF case, the Target automatically
clears the IN bit in the DSCTRL register and leaves the
TLP pointing to the first buffer of the packet; status IS
written to the first buffer and thus the buffer count
bits ARE valid and represent the number of buffers
received up to the time the bad sync was found PLUS the
bad buffer itself. For example, if the Target discovered
a parity error as it was filling up the 5th buffer of a
packet the buffer count would be 5. If 5 buffers were
successfully received and the Target discovered a bad
sync character in the 6th buffer as it was verifying it
before using it, the buffer count would be 6.
2. For outbound packets the following rules apply. First,
it should be noted that Initiators always shut themselves
off (turn off the out bit in the DSCTRL register) and
update the ILP with the address of the FIRST buffer of
the failed packet regardless of the kind of error that
occurred. If the packet is sent successfully the
Initiator will stay enabled as an Initiator and update
the ILP with the thread word of the next packet to be
sent out. Thus, for a successfully sent packet, the
buffer count bits represent the number of buffers in the
sent packet. For an unsuccessfully sent packet, the
buffer count bits represent the number of buffers fetched
SWIFT OPERATION - USER INTERFACE Page 7-13
SWIFT TO USER - CONTROL/STATUS INFORMATION 3 August 1989
UP TO AND INCLUDING the time at which the error occurred.
The only exception to this rule is when a bad sync
character is found in a first buffer (BFB), in which case
there is no status written at all and the buffer count
bits are meaningless. For example, if a sudden DSSI bus
reset occurs while the Initiator is sending out the fifth
buffer of a packet, the buffer count will be 5. If the
Initiator has sent out 5 buffers of a packet and
discovers a bad sync character in the 6th buffer as it is
verifying it to send, the buffer count will be 6 as it
had fetched 6 buffers at the time the error occurred.
- NEB - Not Enough Buffers bit, is set when SWIFT, acting as an
Initiator/Target, expects to send/receive more buffers, but
finds no more buffers linked on.
- MEM - MEMory error bit, is set by SWIFT when it is acting as
an Initiator, has EEN set, and finds an incorrect EDC word at
the end of either the command bytes or the data bytes of a
buffer.
- NRP - No RePly bit, is set when SWIFT gets a selection
timeout, i.e. it tries to select a Target, but no Target
responds.
- NAK - Not AcK bit, is set when the packet was sent or
received unsuccessfully.
- BPH - Bad PHase bit, is set by an Initiator when the Target
has jumped to a phase other than the one expected.
[example 1] A Target has just responded to the selection
phase, but instead of sending the Command Out Phase along
with a REQ, it sends a Status, Data or invalid phase.
[example 2] The Initiator has just received the command
bytes checksum and is expecting the Data Out Phase next,
but gets a Status, Command Out, or invalid phase instead.
[example 3] The Initiator is in the middle of sending the
data bytes and the Target switches to a Status, Command
Out or invalid phase.
[example 4] The Target asserts a Command Out, Data Out or
invalid phase, when the Initiator is expecting the Status
In Phase.
- DSA : target command bytes error bit, is set when the Target
detects an error while receiving the command bytes. This
could be from bad parity, checksum, a Target timeout, or a
DSSI RST occurring while it is in the process of receiving
the command bytes.
SWIFT OPERATION - USER INTERFACE Page 7-14
SWIFT TO USER - CONTROL/STATUS INFORMATION 3 August 1989
- PAR: PARity error bit, is set by a Target when it detects a
parity error, either directly off the DSSI bus, or internal
to SWIFT.
- XSM : Checksum Error Bit, is set when the Target detects a
command or data bytes checksum error.
- SNF : Sync Not Found bit, is set when SWIFT has fetched a
new buffer and either of the sync characters is incorrect.
NOTE
The SYNC characters are setup by the user in EVERY
buffer of the packet, whereas the status word is
written by SWIFT only in the FIRST buffer of the
packet and only upon COMPLETING the packet.
CHAPTER 8
TARGET OPERATION
Introduction
Introduction
SWIFT becomes a target once it responds to selection
by an initiator. When acting as a TARGET, SWIFT
asserts REQs on the DSSI bus when it is ready to
accept data from the initiator. The initiator asserts
ACKs in response to the REQs when it has placed data
on the DSSI bus. Once it has responded to selection,
the target is responsible for controlling all the DSSI
Bus phase changes, using the CD and IO lines. HOW it
updates its TLP register, and IF it writes status to
the status word of the packet, is determined by
whether or not the packet transfer occurred
successfully, and if unsuccessfully, what type of
errors were encountered. Section 1 of this chapter
outlines the steps performed and potential errors
encountered, by a target during a packet transfer.
Section 2 specifies when the target will actually
write buffer status, and how it will update its TLP
register upon completion of a packet. Section 3
contains information on various topics of interest,
regarding SWIFT as a target in general.
8.1 TARGET RECEIVING A PACKET - A STEP BY STEP DESCRIPTION
NOTE
All DSSI bus phases are named as referenced
to the Initiator. Both target and initiator
experience the Status In phase, Data Out
phase etc., even though the target is
actually sending status OUT and taking data
TARGET OPERATION Page 8-2
TARGET RECEIVING A PACKET - A STEP BY STEP DESCRIPTION 3 August 1989
IN. This specification follows the naming
convention specified in the Addendum to DEC
STD 161.
1. SWIFT determines that an initiator is selecting a target when
BSY is deasserted and SEL is asserted on the DSSI bus. It
compares the ID sent by the initiator on the bus, with its
own ID. Once it has determined that IT is being selected, it
responds to the selection by asserting BSY and entering the
COMMAND OUT phase.
NOTE
If the P/R bit in the ID Register is set (1),
SWIFT will use the three low order bits in
the ID Register as its ID. If the P/R bit is
cleared (0), SWIFT will use the three DSSI ID
pins as its ID. If the selected target will
not respond to the selection phase, the
target's ID register and the Destination ID
in the initiator's packet command word,
should be double checked for agreement. The
Selection Enable bit in the target's CSR
should also be checked; if it is not set (1),
the target will not respond to selections and
the initiator could experience a selection
timeout. This checklist is given to aid in
system debug. It does not mean to imply that
a microprocessor has visibility into two
SWIFTs at the same time.
2. Once recognizing that it has been selected, the target
determines if it may fetch the first buffer from buffer
memory. Should either the TLP be zero (0), OR the IN bit not
be set, the target determines that it cannot allow a transfer
and immediately jumps to the Status In phase; it neither
clears the IN bit nor writes status to buffer RAM. If the IN
bit is set and the TLP register is not zero (0), the target
begins to fetch the first buffer. It transfers the starting
address of the buffer, located in the TLP register, into a
microprocessor invisible register called the Current Pointer
Register (CPR). It then begins the check of the buffer:
[a] The target reads the first sync character of the
packet, at the address held in the CPR + 2; this word
should read AAAA Hex, and is the first word the target
uses to determine that the buffer is valid. IF the word
IS NOT correct the target immediately jumps to the Status
In phase, sending a NAK to the initiator. It also clears
the DSCTRL register's MI bit and sets the BFB, IER, LDN
TARGET OPERATION Page 8-3
TARGET RECEIVING A PACKET - A STEP BY STEP DESCRIPTION 3 August 1989
and IBC bits in the ISTAT Register, which interrupts the
micro if enabled to do so. It does not write status to
the status word of the packet, as it does not know if
this is a valid buffer or a part of a previously
completed packet. The target completes the transfer, by
following step 1, outlined in section 8.2 IF the first
sync character IS correct, the target proceeds with step
2b.
[b] The target reads the second sync character, expecting
a 5555 Hex. IF the second sync character IS NOT correct,
the target proceeds the same way it does with a bad first
sync character, outlined in step 2a. If it IS correct,
the target proceeds with step 2c.
[c] The target reads the command word following the
second sync character, and latches the Interrupt on
Completion bit; this bit determines if the target will
interrupt the micro upon the successful completion of a
packet. The Destination ID field of this word is used
only when SWIFT is an initiator, and is ignored by the
target. The target then proceeds with step 3.
3. The target has now determined that the first buffer it
fetched is valid and can begin filling it with the command
bytes that the Initiator is waiting to send. It starts
asynchronously issuing REQs to the Initiator for the command
bytes, and once the first word has been received, begins a
new memory write cycle at address CPR + 8. It begins writing
the command bytes to buffer RAM.
4. When the sixth command byte and the command bytes checksum
have been received, the target checks the command-bytes
checksum; this is the last byte sent by the initiator during
the Command Out Phase:
[a] IF the command bytes checksum IS correct, the target
jumps to the Data In phase and proceeds with step 5.
[b] IF the command bytes checksum IS NOT correct, the
target jumps to the Status In phase and sends a NAK to
the initiator. It also sets the IER and LDN bits in the
ISTAT Register, and interrupts the micro if enabled to do
so. It then writes status to the status word of the
packet, setting the DNE, NAK, DSA, XSM and Buffer Count
bits. The target then completes the transfer, by
following step 2, outlined in section 8.2
TARGET OPERATION Page 8-4
TARGET RECEIVING A PACKET - A STEP BY STEP DESCRIPTION 3 August 1989
5. The target synchronously issues REQS to the initiator for the
data bytes and writes them to buffer memory as they are
received. Once all the data bytes for a given buffer have
been received, the target determines if it has received the
entire packet; if so it continues with step 7. If it needs
to fetch another buffer it continues with step 6.
6. The target has determined that there are more data bytes to
come, and it must fetch a new buffer. It continues to issue
REQs to the initiator until the REQ/ACK offset is reached or
its internal FIFO is filled. Concurrently, it begins a new
memory read cycle, using the address in the CPR; this is the
starting address of the just completed buffer, which contains
the thread word pointing to the address of the next available
buffer linked on. Once the address of the next buffer has
been fetched, it is placed in the CPR, over-writing its
previous contents. The target checks the new address. If
the address is 0, SWIFT DOES NOT have enough buffers
available to complete the packet. It jumps to the Status In
phase and sends a NAK to the initiator. It also sets the
IER, LDN and INB bits in the ISTAT Register, which interrupts
the micro if enabled to do so. The target then writes status
to buffer RAM, setting the DNE, NEB, NAK and Buffer Count
bits. The target completes the transfer by following step 2,
outlined in section 8.2 If the target DOES have another
buffer available, it will use the address in the CPR as a
base address, and issue a new memory read cycle at base
address +2. It then begins the check of the sync characters:
1. IF either of the sync characters IS NOT correct, the
target immediately jumps to the Status In phase, sending
a NAK to the initiator. It also clears the DSCTRL
Register's MI bit and sets the SNF, IER, IBC and LDN bits
in the ISTAT Register, which interrupts the micro if
enabled to do so. As the incorrect sync character was
found in a NON-first packet buffer, the first buffer of
the packet must have been valid, and the target writes
the packet status to it. The target completes the
transfer, by following step 3, outlined in section 8.2
2. If each of the sync characters IS correct, the target
resumes issuing REQs to the initiator. As soon as the
first data word is received, it begins another memory
address cycle at CPR + 16. The target resumes writing
data words to buffer memory as they are received,
returning to step 5.
TARGET OPERATION Page 8-5
TARGET RECEIVING A PACKET - A STEP BY STEP DESCRIPTION 3 August 1989
7. Once the target has received all the data bytes, it checks
the incoming data checksum; this is the last byte of data the
initiator will send during the transfer. If it IS NOT
correct, the target proceeds with step 8. If it IS correct,
the target has received the packet successfully; it jumps to
the Status In phase and sends an ACK to the initiator. The
target then completes the transfer, by following step 4,
outlined in section 8.2
8. IF the data bytes checksum was NOT correct, the target jumps
to the Status Out phase and sends a NAK to the initiator. It
also sets the IER and LDN bits in the ISTAT Register, which
interrupts the micro if enabled to do so. It then writes
status to the status word of the packet, setting the DNE,
NAK, XSM and Buffer Count bits. The target completes the
transfer, by following step 2, outlined in section 8.2
8.2 TARGET COMPLETING A PACKET - 4 MODES
1. When the target finds an incorrect Sync character in the
first buffer, it simply stops the DMA operation on the II bus
and clears the DSCTRL Register's MI bit. It leaves the
address of the first buffer in the TLP register. It jumps
immediately to the Status In phase. Once it has sent the NAK
status to the initiator, it disconnects from the DSSI bus by
deasserting BSY. Finally, it transfers the cleared MI bit to
the IN bit, disabling further target operations until MI has
been set by the micro. The ISTAT Register's BFB bit should
alert the micro that the the sync error was in the first
buffer, and thus the status word of that packet is invalid.
2. When the target receives an incorrect command bytes checksum,
an incorrect data bytes checksum, a command bytes parity
error, a data bytes parity error or does not have enough
buffers to complete a packet, it performs a "burn-one-buffer"
packet ending. It returns a NAK to the initiator, and writes
status to the first buffer of the packet; it does NOT clear
the MI bit. It then updates the TLP register with the
address in the thread word of the FIRST buffer, i.e. the
second buffer, causing it to discard one buffer instead of
several. The second buffer will now be the first buffer of
the next packet it receives. It should be noted that
although the target lost only one buffer due to the transfer
error, the Buffer Count field in the packet status word still
represents the number of buffers that were transferred at the
time the error occurred.
TARGET OPERATION Page 8-6
TARGET COMPLETING A PACKET - 4 MODES 3 August 1989
3. When the target finds an incorrect sync character in a
nonfirst buffer it NAKs the initiator and writes status to
buffer RAM. It also clears the DSCTRL Register's MI bit and
once the NAK has been sent to the initiator, transfers the
cleared MI bit to the IN bit. The target updates the TLP
register with the address of the first buffer of the packet
that failed. The micro should know that status was written
to the first buffer, as the ISTAT Register's SNF bit, rather
than BFB bit was set.
4. When the target successfully receives a packet it writes
status to the first buffer, setting the DNE and Buffer Count
bits. Once it has finished sending the ACK status to the
initiator, it sets the LDN and IDN bits in the ISTAT
Register, which interrupts the micro if the packet command
word's IOC bit, and the CSR's IEN bits were previously set.
Finally, it fetches the address of the next available buffer,
located in the thread word of the last buffer filled, and
places it into the TLP register.
8.3 ADDITIONAL NOTES ON TARGET OPERATION
8.3.1 Target Timeout
The target starts its timer soon after being selected by an initiator.
Should it timeout, the target simply disconnects from the bus by
deasserting BSY. It then sets the LDN and IER bits in the ISTAT
Register, which interrupts the micro if enabled to do so. It then
writes status to the packet it was working on when the timeout
occurred, setting the DNE, NAK and Buffer Count bits. It then updates
the TLP register with the address in the thread word of the FIRST
buffer, performing a "burn-one-buffer" ending. It does not clear the
DSCTRL Register's MI bit, and is capable of being a target again. The
actual timeout value is determined by the value written to the Target
Timeout field of the Timeout Register.
8.3.2 Target Receiving A RST While On The Bus
If a target receives a DSSI RST while it is connected on the DSSI bus,
it will simply disconnect from the bus by deasserting BSY. It will
set the LDN, IER and RST bits in the ISTAT register, which interrupts
the micro if enabled to do so. It then writes status to the packet it
was working on when the RST occurred. Finally, it updates the TLP
register with the address in the thread word of the FIRST buffer, i.e.
the second buffer, performing a "burn-one-buffer" ending. It does not
clear the DSCTRL Register's MI bit and is capable of being a target
again.
CHAPTER 9
INITIATOR OPERATION
Introduction
Introduction
SWIFT will arbitrate for the DSSI bus when the OUT bit
in the DSCTRL Register is set, and the ILP register is
not 0. Once it has arbitrated for the bus and won, it
selects a target and waits for the target to
acknowledge being selected. After that point it acts
like a slave to the target, giving data and ACKs to
the target, ONLY in response to the targets REQS for
data. The target controls all DSSI bus phase changes,
while the Initiator monitors them for validity. HOW
it updates its ILP register, and IF it writes status
to the status word of the packet, is determined by
whether or not the packet transfer occurred
successfully, and if unsuccessfully, what type of
errors were encountered. Section 1 of this chapter
outlines the steps performed and potential errors
encountered, by an initiator during a packet transfer.
Section 2 specifies when the initiator will actually
write buffer status, and how it will update its ILP
register upon completion of a packet. Section 3
contains information on various topics of interest,
regarding SWIFT as an initiator in general.
9.1 INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DESCRIPTION
1. When the ILP register is not 0 and the OUT bit is set, SWIFT
attempts to become an initiator, and arbitrates for the bus.
It asserts BSY and its node ID on the DSSI bus, and after
waiting a period of time, determines if it is the highest ID
on the bus; this is the arbitration phase. If it wins
arbitration, it continues with step 2. If it loses
arbitration it removes BSY and its ID from the BUS, and waits
until the bus is free again before arbitrating again.
INITIATOR OPERATION Page 9-2
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
2. Once the Initiator determines that it has won the DSSI bus,
it asserts SEL on the DSSI bus and prepares to fetch the
first buffer, by copying the address in the ILP register to
the Current Pointer Register (CPR). It then begins fetching
the buffer and checking it for validity:
[a] The initiator reads the first sync character of the
packet, at the address held in the CPR + 2; this word
should read AAAA Hex and is the first word the initiator
uses to determine that the buffer is valid. IF the word
IS NOT correct, the buffer is not valid and the initiator
immediately disconnects from the bus, by deasserting BSY.
All potential targets are totally oblivious to what went
on, as none were ever selected. The initiator also
clears the DSCTRL Register's MO bit, sets the BFB, IER,
and LDN bits in the ISTAT Register, which interrupts the
micro if enabled to do so. It does not write status to
the status word of the packet, as it does not know if
this is a valid buffer or part of a previously completed
packet. The initiator completes the transfer, by
following step 1, outlined in section 9.2 IF the first
sync character IS correct, the initiator continues with
step 2b.
[b] The initiator reads the second sync character,
expecting a 5555 Hex. IF the second sync character IS
NOT correct, the initiator proceeds the same way it does
with a bad first sync character, outlined in step 2a. IF
the second sync character IS correct, the initiator
proceed to step 2c.
[c] The initiator reads the command word, latching the
IOC bit and the three bit Destination ID. The IOC bit
determines if the initiator will interrupt the micro upon
the successful completion of a packet, while the
Destination ID is used to determine which target to
select during the selection phase. The initiator then
continues with step 3.
3. The initiator has now determined that the first buffer of the
packet is valid and begins the target selection phase. It
decodes the three bit Destination ID, and places the
resulting one bit target ID along with its own decoded ID
onto the bus, deasserting BSY soon after. This deassertion
of BSY officially begins the Selection phase, and alerts the
potential target that it should respond by asserting BSY on
the bus. Once BSY is seen by the initiator, it removes SEL
and both IDs from the bus; it is now connected as an
INITIATOR OPERATION Page 9-3
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
initiator. The target is now responsible for maintaining the
connection to the initiator, by maintaining an asserted BSY
on the bus, and controlling the DSSI bus phases via the CD
and IO lines. The initiator proceeds with step 4.
NOTE
If the target does not respond to the
selection phase by asserting BSY on the bus,
a selection timeout could occur. See section
9.3.5 for a description of selection
timeouts.
4. The initiator continues reading the same buffer by fetching
the command bytes. It returns one command byte along with an
ACK, each time a REQ is issued by the target, while
CONCURRENTLY checking the DSSI bus phase generated by the
target:
[a] IF the target is issuing a Status In phase, while the
initiator expects the Command Out phase, the initiator
ACCEPTS the NAK/ACK being sent to it (i.e. acknowledges
the REQ with an ACK); it IGNORES the actual status being
sent, assuming it to be a NAK. It clears the MO bit in
the DSCTRL Register, and sets the LDN and OBC bits in the
ISTAT register, which interrupts the micro if enabled to
do so. It then writes status to the packet, setting the
DNE, NAK, BPH and Buffer Count Bits. The initiator
completes the transfer, by following step 2, outlined in
section 9.2
[b] If the target is issuing an INVALID phase (i.e.
neither the Command Out phase nor the Status In phase),
the Initiator immediately asserts RST on the DSSI bus.
It clears the MO bit in the DSCTRL Register, and sets the
LDN, OBC, RTO and RST bits in the ISTAT register, which
interrupts the micro if enabled. It then writes status
to the packet, setting the DNE, NAK, BPH and Buffer Count
bits. The initiator completes the transfer, by following
step 2, outlined in section 9.2
5. The initiator fetches and sends all of the command bytes from
the first buffer. It then fetches the Command Bytes EDC. If
EDC checking is disabled, i.e. the EEN bit in the CSR is
clear (0), the initiator sends the Command Bytes CHECKSUM
byte to the target. If EEN is set (1), the initiator checks
the EDC first:
INITIATOR OPERATION Page 9-4
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
[a] IF the command bytes EDC IS NOT correct, the
initiator immediately asserts RST on the DSSI bus. It
clears the MO bit in the DSCTRL Register, and sets the
LDN, OBC, RTO and RST bits in the ISTAT register, which
interrupts the micro if enabled to do so. It then writes
status to the packet, setting the DNE, NAK, MEM, and
Buffer Count bits. The initiator completes the transfer,
by following step 2, outlined in section 9.2
[b] IF the command bytes EDC IS correct, the initiator
sends the Command Bytes Checksum to the target and starts
fetching the data bytes from the buffer. It then
continues with step 6.
6. The initiator continues reading the buffer.
NOTE
From the first time an initiator fetches a
new buffer to the point at which the entire
buffer has been sent to the target, the
initiator need only issue one address read
cycle on the memory bus. This is due to the
consecutiveness of the packet header, the
command bytes and the data bytes in the
packet. When an initiator is fetching a new
NON-first buffer, it checks the sync
characters, and then continues reading and
discarding buffer words UNTIL it reaches the
buffer address + 16, the starting point of
valid DATA. At this point it actually starts
transferring the data to the target.
The initiator returns a data byte along with an ACK, for all
REQs that have been issued by the target. It constantly
checks the phase sent out by the target:
[a] IF the target is issuing the Status In phase, while
the initiator expects the Data Out phase, the initiator
ACCEPTS the NAK/ACK being sent to it (i.e. acknowledges
the REQ with an ACK); it and IGNORES the actual status
being sent, assuming it to be a NAK. It clears the MO
bit in the DSCTRL Register and sets the LDN and OBC bits
in the ISTAT register, which interrupts the micro if
enabled to do so. It then writes status to the packet,
setting the DNE, NAK, BPH and Buffer Count Bits. The
initiator completes the transfer, by following step 2,
outlined in section 9.2
INITIATOR OPERATION Page 9-5
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
[b] If the target is issuing an INVALID Phase (i.e.
neither the data phase nor the status phase), the
initiator immediately asserts RST on the DSSI bus. It
clears the MO bit in the DSCTRL Register, and sets the
LDN, OBC, RTO and RST bits in the ISTAT register, which
interrupts the micro if enabled to do so. It then writes
status to the status word of the packet, setting the DNE,
NAK, BPH and Buffer Count bits. The initiator completes
the transfer, by following step 2, outlined in section
9.2
7. The initiator fetches and sends all of the data bytes from
the buffer. It then fetches the data bytes EDC word at the
end of the buffer. If the CSR's EEN bit is NOT set and the
initiator is at the end of the packet, the initiator will
tep
send the target the Data Checksum, then continue with step 9.
If EEN is NOT set and the initiator is NOT at the end of a
packet, the initiator must fetch another buffer, so it
tep
continues with step 8. If EEN IS set, the initiator checks
the EDC first:
[a] IF the data bytes EDC IS NOT correct, the initiator
immediately asserts RST on the DSSI bus. It clears the
MO bit in the DSCTRL Register, and sets the LDN, OBC, RTO
and RST bits in the ISTAT Register, which interrupts the
micro if enabled to do so. It then writes status to the
packet, setting the DNE, NAK, MEM, and Buffer Count bits.
The initiator completes the transfer by following step 3,
outlined in section 9.2
[b] IF the command bytes EDC IS correct, the initiator
continues with step 8 if it has more data to send, or
step 9, if it has no more data to send.
8. The initiator has determined that there are more data bytes
to send and that it must fetch a new buffer. It temporarily
stops acknowledging REQs from the target, and begins a new
memory read cycle, using the address in the Current Pointer
Register (CPR); this is the starting address of the just
completed buffer, which contains the thread word pointing to
the address of the next available buffer linked on. Once the
address of the next buffer has been fetched, it is placed in
the CPR register, over-writing the previous contents. If the
address of the next buffer is 0, SWIFT DOES NOT have another
buffer linked on, even though it believes it has more data to
send. It immediately assert RST on the DSSI bus. It also
sets the LDN, OBC, RST and RTO bits in the ISTAT Register,
which interrupts the micro if enabled to do so. The
INITIATOR OPERATION Page 9-6
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
initiator then writes status to buffer RAM, setting the DNE,
NEB, NAK and Buffer Count bits. The initiator completes the
transfer, by following step 2, outlined in section 9.2 If the
initiator DOES have another buffer linked on, it will use the
address in the Current Pointer Register as a base address,
and issue a new II bus address cycle at base address +2,
beginning the check of the sync characters:
[a] IF either of the sync characters IS NOT correct, the
initiator immediately asserts RST on the DSSI bus. It
also clears the DSCTRL Register's MO bit and sets the
SNF, RST, RTO, OBC and LDN bits in the ISTAT Register,
which interrupts the micro if enabled to do so. As the
invalid sync character was found in a NON-first packet
buffer, the first buffer of the packet must have been
valid, and the initiator writes the packet status to it.
The initiator completes the transfer, by following step
2, outlined in section 9.2
[b] IF each of the sync characters IS correct, the
initiator has fetched a valid buffer and resumes reading
words from buffer memory. It reads and discards the
words until it is up to the address where it is fetching
valid packet DATA (i.e. at CPR + 16). It will then
resume sending data and ACKs, in response to the targets
REQS, cycling back to step 7.
9. The initiator now believes that it has successfully SENT the
entire packet to the target. It waits to receive status from
the target, to see if the target has successfully RECEIVED
the packet. When it receives the REQ from the target to take
the status on the bus, it first checks that the phase being
sent out by the target is actually the Status In phase:
[a] If the target is issuing an INVALID phase, i.e. not
the Status In phase, the initiator will immediately
assert RST on the DSSI bus. It clears the MO bit in the
DSCTRL Register and sets the LDN, OBC, RTO and RST bits
in the ISTAT register, which interrupts the micro if
enabled to do so. It then writes status to the packet,
setting the DNE, NAK, BPH and Buffer Count bits. The
initiator completes the transfer, by following step 2,
outlined in section 9.2
[b] If the target is issuing the Status In phase, the
initiator acknowledges the status (i.e. asserts an ACK
in response to the targets REQ), and checks the status.
IF the status received is an ACK, the initiator sets the
LDN and ODN bits in the ISTAT Register, and interrupts
INITIATOR OPERATION Page 9-7
INITIATOR TRANSFERRING A PACKET - A STEP BY STEP DES ... 3 August 1989
the micro if the packet command word's IOC bit and the
CSR's IEN bit were previously set. It then writes status
to the packet, setting the DNE and Buffer Count Bits.
The initiator completes the transfer, by following step
3, outlined in section 9.2 IF the status received was a
NAK, the initiator clears the MO bit in the DSCTRL
Register and sets the LDN and OBC in the ISTAT register
which interrupts the micro if enabled to do so. The
initiator completes the transfer, by following step 2,
outlined in section 9.2
9.2 INITIATOR COMPLETING A PACKET - 3 MODES
1. When the initiator finds an incorrect sync character in the
first buffer, it simply stops the DMA operation on the II bus
and clears the DSCTRL Register's MO bit. It also updates the
ILP register with the address of the first buffer. Once the
DMA operation has stopped, it transfers the cleared MO bit to
the OUT bit, disabling further initiator operations until MO
has been set by the micro. The BFB bit should alert the
micro that the the sync error was in the first buffer, and
thus the status word of that packet is invalid.
2. When the initiator finds an incorrect sync character in a
nonfirst buffer, not enough buffers to complete a packet, a
bad command bytes or data bytes EDC, an invalid DSSI bus
phase, a read back error on the bus, or it receives a NAK
from the target, it clears the DSCTRL Register's MO bit and
once the status has been written to the status word of the
packet, transfers the cleared MO bit to the OUT bit. It
updates the ILP register with address of the first buffer of
the packet.
3. When the initiator successfully sends a packet and then
receives an ACK status from the target, it updates the ILP
with the starting address of the next packet, found in the
thread word of the last buffer of the current packet. It
does not clear the MO bit, but transfers it to the OUT bit.
9.3 ADDITIONAL NOTES ON INITIATOR OPERATION
INITIATOR OPERATION Page 9-8
ADDITIONAL NOTES ON INITIATOR OPERATION 3 August 1989
9.3.1 Initiator And Fair Arbitration
The Initiator follows a "fair arbitration" scheme when arbitrating for
the DSSI bus. The fair arbitration scheme requires that an initiator
disable itself from arbitrating for the bus for a period of time after
if has just finished transferring a packet; this method allows
"fairer" sharing of the bus between the DSSI devices. For a more
detailed description of the DSSI fair arbitration scheme, the reader
should refer to the Addendum to DEC STD 161.
9.3.2 Initiator Timeout
An initiator timeout is used to Reset a potentially hung DSSI bus.
The initiator timer is started either by a potential initiator when it
wishes to arbitrate for the bus and the DSSI bus is not free (i.e.
either BSY or SEL is asserted), or by an active initiator on the bus.
When the timer expires the initiator asserts RST on the bus for
25usec.
9.3.3 Initiator Receiving A RST While On The Bus.
If an initiator receives a RST while it is transferring a packet on
the bus, it clears the MO bit in the DSCTRL Register. It also sets
LDN and RST in the ISTAT Register and interrupts the micro if enabled
to do so. It then writes status to the status word of the packet it
is currently working on and sets the DNE, NAK and Buffer Count bits.
Finally, it transfers the cleared MO bit to the OUT bit in the DSCTRL
Register.
9.3.4 Initiator Read Back Error Detection
If an initiator detects a read back error while sending data during
the command or data phase of the transfer, it asserts RST on the DSSI
bus. It also clears MO in the DSCTRL Register, and sets the LDN, RST
and RTO bits in the ISTAT Register, which interrupts the micro if
enabled to do so. It then writes status to the status word of the
packet it is currently working on, setting the DNE, NAK and Buffer
Count bits. Finally, it transfers the cleared MO bit to the OUT bit
in the DSCTRL Register.
9.3.5 Initiator Detecting A Selection Timeout
If a device does not respond to the Initiator during the selection
phase of the transfer (i.e. BSY is deasserted and SEL is asserted on
the DSSI bus), a selection timeout could occur. The initiator will
remove its IDs from the bus in a time determined by the selection
INITIATOR OPERATION Page 9-9
ADDITIONAL NOTES ON INITIATOR OPERATION 3 August 1989
timeout bits in the TMO register; a selection abort time later
(defined to be 25.6 usec), the Initiator will remove DSSI_SEL from the
bus. SWIFT will not assert RST on the bus. For a complete
description of selection timeouts, the user should refer to the
Addendum to DEC STD 161. SWIFT clears MO in the DSCTRL Register, and
sets the LDN bit in the ISTAT register, which interrupts the micro if
enabled to do so. It then writes status to the status word of the
packet it is currently working on, setting the DNE, NAK, NRP and
Buffer Count bits. Finally, it transfers the cleared MO bit to the
OUT bit in the DSCTRL Register.
CHAPTER 10
DATA INTEGRITY MEASURES
Errors can occur in several places; SWIFT facilitates recovery from
errors whenever possible. SWIFT supports, but does not require, fault
tolerant operation. This is to allow SWIFT to be used in a non-Cirrus
environment.
10.1 ERROR PROTECTION ON DSSI BUS
SWIFT checks and generates both the DSSI parity and the DSSI checksums
as defined in the DSSI Specification, but SWIFT adds to them another
type of data protection which is compatible with existing devices.
SWIFT reads the DSSI bus while driving it and compares what it reads
to what it thinks it put on the bus. This allows it to do some DSSI
bus error detection without waiting for the target to respond. This
readback provides protection from certain types of noise and bursty
errors which can overwhelm parity and checksums. Reading the bus will
also be useful in testing bondwires in the package, since a broken
bondwire or a bad PC board trace will cause the signal to not pull up
properly. Since there will be a semi-determinate transition time
associated with each line on the bus, SWIFT must be careful when
looking at the bus so as not to look too soon and mistakenly identify
an error. To avoid bus settling problems, SWIFT reads back only the
data it is writing out. It reads the DSSI phase signals off the bus
and uses them to clock the read-back test. Monitoring only the data
lines is sufficient, since there is already much implicit checking of
phase information: if the phase changes at the wrong time, or changes
to the wrong phase at the right time, a DSSI error condition occurs.
10.2 BACKPORT ERROR DETECTION
In order to implement error detection on the Backport, SWIFT checks
the EDC on outgoing buffers and generates EDCs for incoming buffers.
This EDC consists of one word at the end of the first buffer's Command
Bytes and one word after the Data Section of each buffer. SWIFT will
always READ the EDC, but CHECKing of the EDC can be disabled by
clearing the EEN bit in the CSR. SWIFT will always write the correct
EDC for inbound buffers. SWIFT also provides a method by which
DATA INTEGRITY MEASURES Page 10-2
BACKPORT ERROR DETECTION 3 August 1989
erroneous data or address information on the Backport DAL bus can be
guaranteed not to corrupt data during register accesses. This is done
by a combination of register read-back, buffer Sync Characters,
illegal register access detection, and detectable failure modes.
Together, these error detection measures will protect the data in the
buffers and in SWIFT's registers.
10.3 BUFFER PROTECTION
10.3.1 Rotated XOR For Buffer EDCs
Each buffer has two EDCs: a Command Bytes EDC, and a Data EDC. The
EDCs used in the buffers are rotated XORs. The XOR without the
rotation would protect against an odd number of errors in every data
line. The rotation adds more protection against stuck-ats and
intermittently faulty bits.
The Command Bytes EDC covers the 6 Command Bytes in the buffer
header. This is valid only in the first buffer of a packet, since
only the first buffer has valid data in the Command Bytes section.
The Data EDC covers one buffer's Data.
10.3.1.1 How EDCs Are Calculated
Both Command Bytes EDC and Data Bytes EDC are generated the same way.
The calculation begins with a seed value of 0045H. The first word is
XORed with the 0045H. The result is shifted left by 1 bit so that the
MSbit becomes the LSbit. This continues for each of the data words to
be protected by the EDC, with the EDC itself being the rotated result
of the last XOR.
The following is an example of the calculation of the EDC for the
command bytes of a SWIFT buffer.
0045H 0000 0000 0100 0101 ``Seed'' Value
70E0H 0111 0000 1110 0000 First Data Word
----- -------------------
0111 0000 1010 0101 Result of XOR
1110 0001 0100 1010 Result of rotate
00FFH 0000 0000 1111 1111 Second Data Word
----- -------------------
1110 0001 1011 0101 Result of XOR
1100 0011 0110 1011 Result of rotate
0014H 0000 0000 0001 0100 Third Data Word
----- -------------------
1100 0011 0111 1111 Result of XOR
86FFH 1000 0110 1111 1111 Result of rotate - The EDC
DATA INTEGRITY MEASURES Page 10-3
BUFFER PROTECTION 3 August 1989
The following is a segment of C code to calculate an EDC:
unsigned int EDC_CAL(n,a)
unsigned int n ; /* The number of words to be covered by */
/* the EDC */
unsigned int *a ; /* An array holding the n words to be */
{ /* covered by the EDC */
unsigned int edc ; /* The value of the EDC itself */
for (edc = 0x45; n > 0; n--) { /* Count through values in array */
edc ^= *a++ ; /* Do the XOR and inc. array pointer */
if (edc & 0x8000) { /* Check to see if MSbit is set */
edc <<= 1 ; /* Shift left one bit, ``lose'' MSbit */
edc |= 1 ; /* Bring MSbit back into LSbit */
}
else /* MSbit was not set */
edc <<= 1 ; /* Shift left one bit, don't care about */
} /* old MSbit */
return (edc) ;
}
10.3.2 Sync Character Overlapping The Status Word
This helps SWIFT detect wild thread pointers. When SWIFT follows a
thread to a new buffer it checks the Sync Character of that buffer for
a particular pattern, thus reducing the possibility that wild threads
will cause SWIFT to damage memory. The Sync Character is two words
long, each word the complement of the other. This allows SWIFT to
automatically check the DALs for stuck-ats. If a wild thread is
discovered, SWIFT will end the transfer as described in sections 8 and
9. The Sync Character should be "uncommon," e.g., not all zeros, and
different from any possible status word that could be written over it
when the packet has been completed. AAAA5555H satisfies both of these
criteria, and has the added benefit of also being able to detect both
bridges between adjacent data lines and stuck-ats.
10.4 SWIFT REGISTER PROTECTION
SWIFT implements several interlocking methods to protect data
integrity during processor accesses to SWIFT registers. There are
four distinct single bit error modes associated with register
accesses:
1. Bad Address during a register read. This will cause the
processor to read data from the wrong register.
2. Bad Data during a register read. This will cause the
processor to have data with one bit incorrect.
DATA INTEGRITY MEASURES Page 10-4
SWIFT REGISTER PROTECTION 3 August 1989
3. Bad Address during a register write. This will cause the
processor to write to the wrong SWIFT register.
4. Bad Data during a register write. This will cause the data
which is written into a SWIFT register to have one bit
incorrect.
10.4.1 Read Back
When reading data from a SWIFT register, the processor should always
reread the register until it gets the same value twice in a row. This
will protect against all type 1 and 2 errors. Note that during normal
operation SWIFT's registers may change between processor reads, so the
processor may have to be somewhat intelligent in performing
read-backs.
When it is writing data to a SWIFT register, the processor should
always read back the data in the register after writing it. This will
detect all single bit errors on the DAL bus; however, SWIFT acts on
data placed in its registers on a much faster time scale then the
processor, so by the time the processor discovers the mistake, SWIFT
may have already performed an incorrect operation. The following
measures will protect against this type of error.
10.4.2 Register Write Protect
SWIFT's registers are divided into three conceptual classes: Setup,
DSSI Normal Use, and Diagnostics and Testing. The first and last
groups of registers are written to only on powerup or during testing.
Therefore, to prevent an error in the address phase during a write
operation from activating an unanticipated test mode during normal
operation, these two groups of registers can be write protected by a
pair of bits in the DSCTRL Register. If the processor attempts to
write one of these registers while it is protected and the IE and IIA
bits are set, SWIFT will interrupt the processor. If the processor
attempts to write to one of these registers while it is protected and
the IIA bit is clear, SWIFT will not write the register, but will not
set the IAD bit in the ISTAT Register either. On powerup, the write
protect will be clear to allow the processor to configure SWIFT.
10.4.3 Address Separation
All the DSSI Normal Use registers have addresses which are more than
one bit apart. This prevents a single bit error during the address
phase of a write to a SWIFT Normal Use register from adversely
affecting data. There are blank registers which serve to separate
Normal Use registers from each other. Writing to these registers has
DATA INTEGRITY MEASURES Page 10-5
SWIFT REGISTER PROTECTION 3 August 1989
no effect if the IIA bit is clear. Any attempt to access these blank
registers, either read or write, when the IIA bit is set will cause
SWIFT to interrupt the processor but continue with any DSSI operations
which which were already in progress. If the illegal access is a
write, SWIFT will not change anything. If the illegal access is a
read, SWIFT will return a value of 0.
10.4.4 Sync Characters
The Sync Character in the buffer header is used to detect errors in
the data phase of pointer writes. If a pointer gets written
incorrectly and SWIFT starts to act upon it before the processor
discovers the error by readback, or SWIFT reads a bad threadword from
a buffer, SWIFT will discover the error when it checks for the Sync
Character of the new `buffer.' If the incorrect pointer points to an
actual unused buffer, SWIFT will start to process the buffer. If the
buffer is not fully set up to be sent, there should be a checksum
error or a command error. If sending the buffer violates a message's
buffer ordering, the higher level protocols should detect it. In any
case, writing a bad value to a list pointer will have no adverse
effect unless the bad value happens to point to a good buffer or a
chunk of random memory which looks just like a good buffer.
10.4.5 Effects Of Bad Data
One thing the above methods do not protect against is writing
erroneous data to the intended non-pointer register. There are only
two Normal Use non-pointer registers: ISTAT and DSCTRL.
10.4.5.1 Interrupt Status Register
The ISTAT register is write-one-to-clear. This means that the bits in
the register can be set only by SWIFT and can be cleared only by the
microprocessor or a RESET. To clear a bit, the processor writes a one
to it. This allows the processor to read the register, then write the
value it read back into the register to clear it. Writing a zero to a
bit has no effect on it.
If the processor attempts to clear one or more of the bits in the
ISTAT register but a bit gets changed from a one to a zero, the bit,
and the interrupt it represents, will remain pending until the read
back, so no harm is done. If one of the bits is inadvertently
cleared, the effects are determined by which bit is affected, but, in
general, will not corrupt existing good data.
If the processor reads the ISTAT register at the beginning of the
interrupt service routine, handles the interrupts, rechecks the ISTAT
register for new interrupts, then clears all of the bits in the ISTAT
DATA INTEGRITY MEASURES Page 10-6
SWIFT REGISTER PROTECTION 3 August 1989
at the same time, then unintentionally clearing an ISTAT bit will not
be a problem.
10.4.5.2 DSSI Control Register
The DSCTRL Register controls the status of the pointer lists and the
write enable on the non-Normal Use registers. Only the IN, MI OUT,
MO, WP1, and WP2 bits are writable; all other bits in the DSCTRL
Register are read-only. The IN and MI, and OUT and MO, bits are
enable-pairs for the inbound buffer list, and outbound buffer list,
respectively. If both bits of each pair are not written with the same
value, neither control bit will not be affected by the write. The WP1
and WP2 bits are a protect-pair for the register write protect of the
non-Normal-Use registers. If either of these bits has a 1 written to
it, the write protection is activated, but both must be cleared to
deactivate it. IIP and OIP, which are both read-only, are provided so
the processor can tell when SWIFT is transferring a packet on the DSSI
bus.
CHAPTER 11
ARBITRATING MODE
A second backport mode was added for the TF family of products. This
mode incorporates some additional functionality, and makes some
assumptions about the external hardware. These assumptions include:
1. Other hardware residing on the II bus is not "bursty" (i.e.
single accesses).
2. Other hardware rarely accesses the memory bus (low
throughput).
3. Memory access times are faster than 150 ns.
4. An external counter having a "LOAD" and "CLK" input is used.
5. There is no more than 128kB of memory.
This set of assumptions fits nicely with the architecture of a tape
drive. This mode, however, is not meant for devices with two or more
high throughput ports, such as a disk drive or adapter.
11.1 ADDITIONAL FUNCTIONALITY
11.1.1 Memory Arbitration
SWIFT will handle the arbitration of the memory bus. Other hardware
will request this bus from SWIFT by asserting HP_BUSREQ(HP_RDY).
After the current cycle (or immediately if the SWIFT is idle), SWIFT
will relinquish the bus by tristating its data bus and signal this by
asserting HP_BUSGRANT. The SWIFT will continue to assert HP_BUSGRANT
until the requesting device has deasserted HP_BUSREQ. These requests
must be short in duration and infrequent if SWIFT throughput is not to
be degraded. While SWIFT is bus master, it assumes it controls the
memory and will never be held off. Therefore, all data cycle will be
of fixed 150 ns. duration.
ARBITRATING MODE Page 11-2
ADDITIONAL FUNCTIONALITY 3 August 1989
11.1.2 Address Counter Control
SWIFT will generate the control signals needed to use an external
counter with no "glue" chips. In this mode, HP_ADDR16 becomes the
HP_LOAD signal (see following section on addressing). As such, it is
asserted while the address is on SWIFT DAL lines. HP_AS becomes the
counter clock(HP_CTRCLK). It is asserted in the center of the LOAD
signal.
11.1.3 Reduced Address Capability
In order to provide the above mentioned functionality, the SWIFT uses
an address line (HP_ADDR16) as a control signal. The effect of this
is a 50% reduction in the amount of memory the SWIFT is able to
address. The highest order address bit (address bit 17) is no longer
sent from the chip. In its place on HP_DAL<0> is address bit 16.
CHAPTER 12
TEST STRATEGY
SWIFT was designed with testability in mind. Towards that end, there
are several features implemented in SWIFT to aid in testing the chip.
When SWIFT is in diagnostic mode, the processor will be able to test a
large percentage of the internal circuitry, as well as various
interconnects on the module. This allows a large degree of in-circuit
testing without any special hardware.
12.1 LOOP BACK TESTING
When LPB is set in the DICTRL register, SWIFT is in internal loopback
mode. In this mode, the processor is able to directly control the
DSSI inputs to SWIFT. It is also able to read the outputs which the
chip generates. This is accomplished by diverting I/O activity away
from the physical DSSI port to the DDB and DCS registers. When in
internal loopback mode, SWIFT does not drive the physical DSSI bus,
nor does it respond to signals on the physical DSSI bus. This allows
a large part of SWIFT to be tested while it is connected to an active
DSSI bus or not connected to anything. In internal loopback mode, the
processor can simulate both inbound and outbound transfers. To
perform a transfer in internal loopback mode, the processor must link
up the appropriate buffers and set up the SWIFT in the normal fashion,
except LPB must be set and PRE should be clear if the SWIFT is
connected to an active DSSI bus. The SWIFT will then either send or
receive a packet through the DCS and DDB registers, with the processor
acting as the other node in the transfer.
Note that DCS and DDB are not storage registers; what is read
from them is not necessarily what was last written to them.
Specifically, when in internal loopback mode, what is read from the
DCS and DDB registers represents only what the SWIFT is driving on the
DSSI bus; however, due to the way the DCS register is connected to the
control signals, in addition to the signals you would expect the SWIFT
to assert, there may be other signals asserted. This will be
explained in greater detail below. Reading the DDB or DCS does not
necessarily show any bits which were driven by the processor by a
previous write to the DDB or DCS register. For example, if the
processor writes a 0003H to the DDB, then reads the DDB and sees
0004H, this means that the DSSI data bus has the 3 low order bits
TEST STRATEGY Page 12-2
LOOP BACK TESTING 3 August 1989
asserted, with bit 2 asserted by the SWIFT and bits 0 and 1 asserted
by the processor and representing other nodes on the DSSI bus. This
situation could occur during arbitration if the SWIFT's ID is 2.
Since register accesses work on a different time scale than some
of the operations on the DSSI bus, problems could occur when control
through the DDB and DCS registers is not fast enough to meet DSSI bus
timing. Fortunately, there is only one case where this is a major
problem, and SWIFT has an interlock feature when in internal loopback
mode which solves it. In normal operation, during the data phase of
an inbound transfer SWIFT can issue up to seven REQs without receiving
an ACK (see REQ/ACK offset). Since the cycle time for issuing REQs is
much faster than a register access time, in internal loopback mode
SWIFT could have issued several REQs that the processor could not
detect through reading the DCS register. To solve this potential
problem, SWIFT has an interlock when in internal loopback mode which
prevents it from deasserting REQ or ACK until the DDB register is
accessed and the normal conditions for deassertion are met. Use of
this interlock is described below.
Since, when in internal loopback mode, SWIFT gets its DSSI input
only from the DCS and DDB registers, it cannot read back the values it
is writing to the DSSI bus. This would cause a read back error during
command or data phases, but another interlock prevents all read back
errors during internal loopback mode. This has the side effect that
the processor cannot simulate a read back error when the SWIFT is in
internal loopback mode by writing an incorrect value to the DDB.
Another operation affected by the lack of data read back in internal
loop back mode is arbitration. The circuitry that decides if the
SWIFT has won arbitration expects to see the SWIFT's encoded ID on the
bus; if it does not, it will assume that the SWIFT has lost
arbitration. To remedy this situation, the processor must write to
the DDB the encoded ID of the SWIFT if the SWIFT is to win arbitration
and act as an initiator. In the case where the SWIFT is to act as a
target, no special action need be taken, since the SWIFT will lose
anyway, but the encoded ID of the SWIFT can be asserted by the
processor along with its own encoded ID when it writes to the DDB
during the arbitration phase. The processor can then read the DDB to
verify that the SWIFT is putting out its ID for arbitration.
12.1.1 SWIFT As An Initiator
If the SWIFT is to be acting as the initiator, the processor should
first initialize SWIFT and have buffers containing a packet linked
into the ILP. Before the processor enables the SWIFT by writing to
the DSCTRL register, it should write to the DDB register the encoded
ID of the SWIFT. This is to let the SWIFT see its own ID during
arbitration. The processor could "OR" the value it writes to the DDB
with a lower encoded address to simulate other nodes arbitrating and
losing, or it could "OR" the value with a higher encoded address to
simulate losing arbitration. Note that it is always the processor's
responsibility to generate the parity bit when it writes to the DDB.
TEST STRATEGY Page 12-3
LOOP BACK TESTING 3 August 1989
After writing the DSCTRL register, the processor can read the DDB
register to verify that the SWIFT is putting out the correct data.
The processor then should read the DCS register until it has only the
SEL bit set (value of 0020H). Once the processor sees this, it should
read the DDB register to verify that the SWIFT is generating the
correct selection data. The processor should then write BSY and C/D
(0042H) to the DCS register to put the transfer into command phase.
The following is done for each of the six command bytes and the
checksum:
1. The processor writes BSY, REQ, and C/D (0046H) to the DCS to
issue the REQ to the SWIFT.
2. The processor reads the DCS register until the SWIFT asserts
ACK. The SWIFT will also be asserting REQ and C/D, so the
processor should be looking for 000EH.
3. Once it sees ACK asserted, the processor should deassert REQ
by writing only BSY and C/D (0042H) to the DCS register.
4. The processor then reads the DDB register both to verify the
command byte and allow the SWIFT to deassert the ACK.
5. The processor reads the DCS register until the SWIFT
deasserts ACK. The SWIFT will also deassert REQ, but will
leave C/D asserted, so the processor should be checking for
0002H.
After completing the transfer of the Command Bytes Checksum, the
processor should write only BSY (0040H) to the DCS register to put the
transfer into the Data Phase. Then, for each of the Data Bytes and
the Data Bytes Checksum, the processor should do the following:
1. Write BSY and REQ (0044H) to the DCS register.
2. Write just BSY (0040H) to the DCS register. These two writes
issue a REQ to the SWIFT. The processor may issue as many
REQs as the REQ/ACK offset allows before doing the next step.
3. For each REQ issued, the processor should watch for an ACK in
the DCS register. The C/D bit will also always be set, and
the REQ bit will be set only if the the processor still has
REQ asserted, so the processor should be looking for either
000CH or 00EH.
4. Once the ACK bit is set, the processor should read the DDB.
This will return the value of the data byte and will allow
the SWIFT to deassert ACK.
5. If there have been more REQs issued than ACKs received, the
processor can watch for another ACK then read the DDB, but it
should be noted that the processor may not be able to see the
deassertion of ACK because it can happen faster than a
register cycle.
TEST STRATEGY Page 12-4
LOOP BACK TESTING 3 August 1989
6. If the number of REQs and ACKs are equal, the processor may
read the DCS register to verify that the SWIFT deasserted
ACK.
After the Data Bytes Checksum, the processor puts the transfer into
Status In phase by asserting BSY, C/D, and I/O (0043H) in the DCS
register. It then writes the status of the transfer (0061H for an
ACK, anything else for a NACK) to the DDB register, then asserts BSY,
REQ, C/D, and I/O (0047H) in the DCS register. It then watches the
DCS register for ACK. REQ, C/D and I/O will also get asserted, so the
processor should watch for 000FH. The processor then removes ACK by
writing 0043H to the DCS register. It can then check the DCS register
to verify that only C/D and I/O are asserted (0003H). Finally, the
processor clears all bits in the DCS register, and the DSSI portion of
the transfer is completed. It will still take some time for the SWIFT
to complete the transfer, so the processor should watch for the SWIFT
to write the status to the Status Word in the first buffer.
12.1.2 SWIFT As A Target
If the SWIFT is to be used as a target, the processor should first
initialize the SWIFT and have empty buffers linked into the TLP. It
then puts the encoded address of the SWIFT and its own encoded address
into the DDB. This is used for arbitration and selection. The
processor then asserts BSY in the DCS register (0040H). This begins
the Arbitration Phase. It then asserts BSY and SEL in the DCS
register (0060H). This begins the Selection Phase. The processor
then releases BSY, but leaves SEL asserted (0020H). The processor
then waits for the SWIFT to assert BSY and C/D (0042H). Once the
SWIFT has asserted BSY and C/D, the processor should release SEL by
writing 0000H to the DCS register. The processor then does the
following for each of the six Command Bytes and the Command Bytes
Checksum:
1. Watch for SWIFT's assertion of REQ. SWIFT will also have
BSY, ACK, and C/D set, so the processor should look for
004EH.
2. Write the data byte to the DDB.
3. Write an ACK to the DCS (0008H).
4. Read the DDB. This is to allow the SWIFT to deassert REQ
(see above).
5. (optional) Read the DCS to verify that REQ is deasserted.
This is optional because if the SWIFT does not deassert REQ,
something is very wrong and it will be caught later in the
tests.
TEST STRATEGY Page 12-5
LOOP BACK TESTING 3 August 1989
6. Deassert ACK by writing 0000H to the DCS register.
After the Command Bytes Checksum, the processor watches for C/D to
become deasserted. BSY will also be asserted, and REQ and ACK may or
may not be asserted, so the processor should look for 0040H or 004CH.
The processor then does the following for each of the Data Bytes and
the Data Bytes Checksum:
1. Watch for SWIFT's assertion of REQ. SWIFT will also have BSY
and ACK asserted, so the processor should look for 004CH.
2. Write the Data Byte to the DDB register
NOTE
At this point, the processor should not
attempt to verify that SWIFT has deasserted
REQ since it may reassert REQ before the
processor can read the DCS register.
3. Assert ACK by writing 0008H to the DCS register.
4. Deassert ACK by writing 0000H to the DCS register.
After the Data Bytes Checksum, the processor watches for CMD, BSY,
I/O, REQ, and ACK (004FH) in the DCS register. This will indicate
that the SWIFT has gone into Status Phase and has the status ready in
the DDB. The processor now reads the status from the DDB, then
asserts ACK in the DCS register (0008H) to acknowledge receipt of the
packet status. It then reads the DDB again to allow the SWIFT to
deassert REQ, then reads the DCS to verify that the SWIFT has
deasserted REQ. Finally, the processor deasserts all DSSI control
signals by writing 0000H to the DCS.
12.2 EXTERNAL CONNECTOR TESTING
A second test procedure involves using an external connector at the
DSSI bus. This allows the processor to verify the functionality of
the DSSI bus drivers and receivers and the signal paths to the
connector. Bits in the DICTRL register allow the processor to enable
various DSSI drivers. Using the DDB and DCS registers, the processor
can drive the DSSI bus. Reading these registers should show the
values which were written. Note that this external connector must
contain the proper terminators and be powered. The procedure for
testing the SWIFT's DSSI port drivers and receivers is:
1. The external connecter is attached to the DSSI Port.
2. The processor asserts DOE, DIA and PRE by writing 0013H to
the DICTRL register.
TEST STRATEGY Page 12-6
EXTERNAL CONNECTOR TESTING 3 August 1989
3. The processor writes 0155H to the DDB.
4. The processor reads the DDB register. The value read should
be 0155H.
5. The processor writes 00AAH to the DDB.
6. The processor reads the DDB register. The value read should
be 00AAH.
7. The processor clears DOE and asserts COE and DIA by writing
0009H to the DICTRL register.
8. The processor writes 0055H to the DCS.
9. The processor reads the DCS register. The value read should
be 0055H.
10. The processor writes 002AH to the DCS.
11. The processor reads the DCS register. The value read should
be 002AH.
12. The processor deasserts COE and DIA by writing 0000H to the
DICTRL register.
13. The external connector is removed from the DSSI port.
12.3 OTHER TESTABILITY FEATURES
The loopback and external tests mentioned above are intended for
in-circuit testing of the SWIFT. There are also a few features
intended to simplify fault-grading and manufactoring tests.
12.3.1 Test Bit In DICTRL
The Test bit causes certain counters in the SWIFT to count faster than
they normally would. This allows testing of conditions during
fault-grading which normally would use a prohibitively large number of
vectors, such as timeouts and DSSI bus Resets.
12.3.2 SRD Bit In DICTRL
Assertion of the SRD bit causes the ISTAT register to behave as a R/W
register. This is to allow fault-grading of the bits in the ISTAT
register without simulating every condition.
TEST STRATEGY Page 12-7
OTHER TESTABILITY FEATURES 3 August 1989
12.3.3 LOTC And BC
These registers provide visibility into two counters which are used in
SWIFT. This visibility allows fault-grading of the counters without
having to count through all the bits in the counters.
CHAPTER 13
EXTERNAL OPERATIONS AND TIMING
This section discusses the external interfaces of SWIFT, especially to
the memory port. Diagrams are added for clarity.
13.1 MICROPROCESSOR READ CYCLES
When the microprocessor wishes to read the contents of a SWIFT
register, it asserts HP_CS. Upon detection of this signal, SWIFT will
finish any memory transaction currently in progress and service the
microprocessor. The time that can elapse during this period is
variable; it depends greatly on the memory bus activity. In the best
case (the memory port is idle), the assertion of HP_ADREN could be as
soon as 100 ns. following the assertion of HP_CS. In the worst case
(SWIFT has just begun a new memory cycle or is updating a pointer
register), the microprocessor is forced to sit idle as SWIFT asserts
HP_AS, followed by HP_DS to the memory. The duration of this action
is a function of memory bandwidth and traffic and will not be
estimated here. One clock before the assertion of HP_ADREN, SWIFT
will release the HP_WRITE signal, preparing for the microprocessor
access. Upon the assertion of HP_ADREN, the external logic must begin
to drive the register address onto the HP_DAL lines and also drive
HP_WRITE. At this time, the external logic may deassert HP_CS. One
HP_CLK cycle following the assertion of HP_ADREN, SWIFT will assert
HP_AS. This does not require any reaction by the external logic.
Note that this does not happen in the arbitrating mode. Three clocks
later, SWIFT will deassert HP_ADREN, thereby ending the address
portion of the cycle. SWIFT will latch the contents of the HP_DAL
lines internally, along with the HP_WRITE signal. The external
hardware may release HP_WRITE now. SWIFT requires no hold time on
either address or HP_WRITE. Four clock cycles later, SWIFT will
assert the HP_DATAEN signal. The SWIFT will also drive the contents
of the selected register onto the HP_DAL lines. One clock cycle
later, SWIFT will deassert HP_AS. This signals the external logic to
release HP_WRITE if it hasn't already done so. Three clock cycles
later, SWIFT will deassert the HP_DATAEN signal, thereby ending the
cycle. Data, however, will remain on the HP_DAL lines for an
additional clock cycle or until the deassertion of HP_CS, whichever is
later.
EXTERNAL OPERATIONS AND TIMING Page 13-2
MICROPROCESSOR READ CYCLES 3 August 1989
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
HP_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
(input) | | | | |
|T1 | | | |
| _____________|_______________|_______________|___
HP_WRITE L----|-/ |\--------------|---------------|---\-------
| ||T2 | |
___ | _____|_______________|_______________|___________
HP_CS L |\__|_________/_____|_______________|_______________|___/
(input) | | | | | | |
| | |T4 | |T5 | |
| T3 | | | |
| | | |
_________ |_____________|_______________|___________
HP_ADREN L |\_____________/| | |
(output) | | | | |
| T6 | | |T8 |
| | | | | |T9
| | T7 | | |
_________________________________________ __________
HP_DATAEN L | | |\_____________/|
(output) | | | |
|T10| | | T11 |
______________ | | ____________|_________
HP_AS L |\__________________________|__/| |
(output) | | | | |
| | |T13| |
| T12 | |T14|
| | |
| | T15 | |
_________ | _________ | | ________
HP_DAL H _________< ADDRESS >_________< DATA OUT >________
(BiD)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-3
MICROPROCESSOR READ CYCLES 3 August 1989
+-------+---------------------------------------+---------------+
| Name | Description | Time |
+-------+---------------------------------------+---------------+
| T1 | HP_CLK cycle time | T (33 ns. min)|
+-------+-------------------------------------------------------+
| T2 | HP_WRITE hold time following HP_ADREN | 0 |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T3 | HP_CS assertion to HP_ADREN assertion| no max |
+-------+-------------------------------------------------------+
| T4 | HP_CLK rising to HP_ADREN assertion | 20 ns max |
+-------+-------------------------------------------------------+
| T5 | HP_CLK rising to HP_ADREN deassertion | 27 ns max |
+-------+---------------------------------------+---------------+
| T6 | HP_ADREN assertion width | 4T-6 min |
+-------+---------------------------------------+---------------+
| T7 | HP_ADREN deassertion to HP_DATAEN | 4T-6 min |
| | assertion | |
+-------+---------------------------------------+---------------+
| T8 | HP_CLK rising to HP_DATAEN assertion | 20 ns min |
+-------+---------------------------------------+---------------+
| T9 |HP_CLK rising to HP_DATAEN deassertion | 27 ns min |
+-------+---------------------------------------+---------------+
| T10 | HP_ADREN assertion to HP_AS assertion | T-5 min |
+-------+---------------------------------------+---------------+
| T11 | HP_DATAEN assertion width | 4T-6 min |
+-------+---------------------------------------+---------------+
| T12 | HP_AS assertion width | 8T-5 min |
+-------+---------------------------------------+---------------+
| T13 | HP_DATAEN assertion to HP_AS | T-5 max |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T14 | Data hold time after HP_DATAEN | T-15 min |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T15 | address hold time after HP_ADREN | 0 |
| | deassertion | |
+-------+---------------------------------------+---------------+
13.2 MICROPROCESSOR WRITE CYCLES
When the microprocessor wishes to modify the contents of a SWIFT
register, it asserts HP_CS. Upon detection of this signal, SWIFT will
finish any memory transaction currently in progress and service the
microprocessor. The time that can elapse during this period is
variable; it depends greatly on the memory bus activity. In the best
case (the memory port is idle), the assertion of HP_ADREN could be as
soon as 100 ns. following the assertion of HP_CS. In the worst case
(SWIFT has just begun a new memory cycle or is updating a pointer),
the microprocessor is forced to sit idle as SWIFT asserts HP_ AS,
followed by HP_DS to the memory. The duration of this action is a
function of memory bandwidth and traffic and will not be estimated
EXTERNAL OPERATIONS AND TIMING Page 13-4
MICROPROCESSOR WRITE CYCLES 3 August 1989
here. One clock before the assertion of HP_ADREN, SWIFT will release
the HP_WRITE signal, preparing for the microprocessor access. Upon
the assertion of HP_ADREN, the external logic must begin to drive the
register address onto the HP_DAL lines and also drive HP_WRITE. At
this time, the external logic can deassert HP_CS. One HP_CLK cycle
following the assertion of HP_ADREN, SWIFT will assert HP_AS. This
does not require any reaction by the external logic. This does not
happen in the arbitrating mode. Three clock cycles later, SWIFT will
deassert HP_ADREN, thereby ending the address portion of the cycle.
SWIFT will latch the contents of the HP_DAL lines internally, along
with the HP_WRITE signal. Four clock cycles later, SWIFT will assert
the HP_DATAEN signal. The external logic may drive the contents of
the selected register onto the HP_DAL lines. One clock cycle later,
SWIFT will deassert HP_AS. This signals the external logic to release
HP_WRITE, if it hasn't done so already. Three clock cycles later,
SWIFT will deassert the HP_DATAEN signal, thereby ending the cycle.
Data will be latched into SWIFT upon the deassertion of HP_ DATAEN.
No hold time is required by SWIFT.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
HP_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
(input) | | | | |
|T1 | | | |
| | | |
HP_WRITE L----|-\_____________|/--------------|---------------|---/-------
| ||T2 | |
___ | _____|_______________|_______________|___________
HP_CS L |\__|_________/_____|_______________|_______________|___/
(input) | | | | | | |
| | |T4 | |T5 | |
| T3 | | | |
| | | |
_________ |_____________|_______________|___________
HP_ADREN L |\_____________/| | |
(output) | | | | |
| T6 | | |T8 |
| | | | | |T9
| | T7 | | |
_________________________________________ __________
HP_DATAEN L | | |\_____________/|
(output) | | | |
|T10| | | T11 |
______________ | | ____________|_________
HP_AS L |\__________________________|__/| |
(output) | | | | |
| | |T13| |
| T12 | |T14|
| | |
| | T15 | |
_________ | _________ | | ___
HP_DAL H _________< ADDRESS >_________< DATA IN >___
(BiD)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-5
MICROPROCESSOR WRITE CYCLES 3 August 1989
+-------+---------------------------------------+---------------+
| Name | Description | Time |
+-------+---------------------------------------+---------------+
| T1 | HP_CLK cycle time | T (33 ns. min)|
+-------+-------------------------------------------------------+
| T2 | HP_WRITE hold time following HP_ADREN | 0 |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T3 | HP_CS assertion to HP_ADREN assertion| no max |
+-------+-------------------------------------------------------+
| T4 | HP_CLK rising to HP_ADREN assertion | 20 ns min |
+-------+-------------------------------------------------------+
| T5 | HP_CLK rising to HP_ADREN deassertion | 27 ns min |
+-------+---------------------------------------+---------------+
| T6 | HP_ADREN assertion width | 4T-6 min |
+-------+---------------------------------------+---------------+
| T7 | HP_ADREN deassertion to HP_DATAEN | 4T-6 min |
| | assertion | |
+-------+---------------------------------------+---------------+
| T8 | HP_CLK rising to HP_DATAEN assertion | 20 ns min |
+-------+---------------------------------------+---------------+
| T9 |HP_CLK rising to HP_DATAEN deassertion | 27 ns min |
+-------+---------------------------------------+---------------+
| T10 | HP_ADREN assertion to HP_AS assertion | T-5 min |
+-------+---------------------------------------+---------------+
| T11 | HP_DATAEN assertion width | 4T-6 min |
+-------+---------------------------------------+---------------+
| T12 | HP_AS assertion width | 8T-5 min |
+-------+---------------------------------------+---------------+
| T13 | HP_DATAEN assertion to HP_AS | T-5 max |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T14 | Data hold time after HP_DATAEN | 0 |
| | deassertion | |
+-------+---------------------------------------+---------------+
| T15 | address hold time after HP_ADREN | 0 |
| | deassertion | |
+-------+---------------------------------------+---------------+
Additional critical times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-6
MICROPROCESSOR WRITE CYCLES 3 August 1989
+-----------------------------------------------+-------+-------+
| Parameter | min | max |
+-----------------------------------------------+-------+-------+
| HP_ADREN asserted to address must be valid | 0 | 2T+15 |
+-----------------------------------------------+-------+-------+
| HP_ADREN deasserted to address invalid on bus | 0 | |
+-----------------------------------------------+-------+-------+
| HP_ADREN asserted to HP_WRITE valid | 0 | 2T+15 |
+-----------------------------------------------+-------+-------+
| HP_ADREN deasserted to HP_WRITE invalid | 0 | |
+-----------------------------------------------+-------+-------+
| HP_DATAEN asserted to HP_DAL valid (READ) | | 25 |
+-----------------------------------------------+-------+-------+
| HP_DATAEN asserted to data must be valid | | 2T |
| (WRITE) | | |
+-----------------------------------------------+-------+-------+
| HP_DATAEN deasserted to data invalid (WRITE) | 0 | |
+-----------------------------------------------+-------+-------+
| HP_CS deassertion time | 5T | |
+-----------------------------------------------+-------+-------+
13.3 MEMORY READ CYCLES (NORMAL MODE)
When SWIFT wishes to begin a new transfer, it places the address of
the memory location onto the HP_DAL lines. Three clock cycles later,
HP_AS is asserted. This indicates to the external logic that SWIFT is
beginning a new cycle. The external logic must latch the address on
the asserting edge of HP_AS. Three clock cycles later, SWIFT will
withdraw the address from the multiplexed bus. One clock tick later,
SWIFT will assert HP_DS. This signals that SWIFT wishes to read a
memory location. This pulse will last a minimum of 160 ns., although
it can be made longer. SWIFT monitors the HP_RDY signal waiting for
its assertion. Once this is seen, SWIFT is free to end the current
HP_DS. Following the deassertion of the first data strobe, SWIFT will
deassert HP_AS. For each additional contiguous word SWIFT needs, it
will assert only HP_DS. (The HP_AS signal is used to select a new
starting address and is not needed on a per access basis.) SWIFT will
not reassert HP_DS if the HP_RDY from the previous HP_DS is still on
the bus. If the microprocessor wishes to access a SWIFT register
while a DMA operation is in progress, SWIFT will finish the data
strobe currently asserted and service the microprocessor. Following
this, SWIFT will NOT issue a new address strobe and will expect the
external logic to continue from the address which was last read.
EXTERNAL OPERATIONS AND TIMING Page 13-7
MEMORY READ CYCLES (NORMAL MODE) 3 August 1989
_ _ _ _ _ _ _ _ _ _ _ _
SYS_CLK H__| |_| |...._| |_| |........_| |_| |_| |_| |_| |_| |_| |_| |_
(input)
|T1 | | |
| | |
|T2| | |
______| | | ____________________________
HP_AS L |\_______|_______________|___/
(output) | | |
| T3 | T4 | | |
| |_|______ | __________________
HP_DAL H< ADDRESS >_|______< DATA IN >__________________< DATA IN
(BiD) | | |T7|
| |T5 | |
_________________ | T6 |_____________________
HP_DS L \______________/ \_________
| | T8 |
| T9 |
________________________________|_______________________________
HP_WRITE L | |
(output) | | T10 |
|T11 |
______________________ ________________________________
HP_RDY \________/
(input)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-8
MEMORY READ CYCLES (NORMAL MODE) 3 August 1989
+-------+-----------------------------------------------+-------+
| Name | Description | Time |
+-------+-----------------------------------------------+-------+
| T1 | SYS_CLK cycle time | 33 ns |
+-------+-----------------------------------------------+-------+
| T2 | SYS_CLK rising to HP_AS assertion (max) | 25 ns |
+-------+-----------------------------------------------+-------+
| T3 | Address Valid to HP_AS assertion (min) | 72 ns |
+-------+-----------------------------------------------+-------+
| T4 | Address Hold after HP_AS assertion (min)| 78 ns |
+-------+-----------------------------------------------+-------+
| T5 | SYS_CLK rising to HP_DS assertion (max) | 21 ns |
+-------+-----------------------------------------------+-------+
| T6 | Data setup to HP_DS deassertion (min) | 40 ns |
+-------+-----------------------------------------------+-------+
| T7 | Data hold after HP_DS deassertion (min) | 0 ns |
+-------+-----------------------------------------------+-------+
| T8 | Data Strobe deassertion time (minimum) | 225 ns|
+-------+-----------------------------------------------+-------+
| T9 | Data Strobe assertion time (minimum) | 160 ns|
+-------+-----------------------------------------------+-------+
| T10 | HP_RDY assertion to HP_DS deassertion (min) | 66 ns|
+-------+-----------------------------------------------+-------+
| T10 | HP_RDY assertion to HP_DS deassertion (max)* | 100 ns|
+-------+-----------------------------------------------+-------+
| T11 | HP_RDY assertion after HP_DS assertion | 60 ns |
| | to insure 400 ns. cycle time (max) | |
+-------+-----------------------------------------------+-------+
* If HP_RDY is asserted within the first 60 ns. of HP_DS, the
data strobe will be 160 ns. long. The timing parameter, T10,
refers to the synchronization delay if HP_RDY is NOT asserted
within the first 60 ns.
13.4 MEMORY WRITE CYCLES (NORMAL MODE)
When SWIFT wishes to begin a new transfer, it places the address of
the memory location onto the HP_DAL lines. Three clock cycles later,
HP_AS is asserted. This indicates to the external logic that SWIFT is
beginning a new cycle. The external logic must latch the address on
the asserting edge of HP_AS. Three clock cycles later, SWIFT will
withdraw the address from the multiplexed bus. One clock tick later,
SWIFT will assert HP_DS. This signals that SWIFT has placed the data
onto the DAL lines. This pulse will last a minimum of 160 ns.,
although it can be made longer. SWIFT monitors the HP_RDY signal
waiting for its assertion. Once this is seen, SWIFT is free to end
the current HP_DS. Following the deassertion of the first data
strobe, SWIFT will deassert HP_AS. For each additional contiguous
word SWIFT needs, it will assert only HP_DS. (The HP_AS signal is
used to select a new starting address and is not needed on a per
access basis.) SWIFT will not reassert HP_DS if the HP_RDY from the
previous HP_DS is still on the bus. If the microprocessor wishes to
EXTERNAL OPERATIONS AND TIMING Page 13-9
MEMORY WRITE CYCLES (NORMAL MODE) 3 August 1989
access a SWIFT register while a DMA operation is in progress, SWIFT
will finish the data strobe currently asserted and service the
microprocessor. Following this, SWIFT will NOT issue a new address
strobe and will expect the external logic to continue from the address
which was last written.
_ _ _ _ _ _ _ _ _ _ _ _
SYS_CLK H__| |_| |...._| |_| |........_| |_| |_| |_| |_| |_| |_| |_| |_
(input)
|T1 | | |
| | |
|T2| | |
______| | | ____________________________
HP_AS L |\_______|_______________|___/
(output) | | |
| T3 | T4 | | |
| |_|______ | __________________
HP_DAL H< ADDRESS >_|______< DATA OUT >__________________< DATA OU
(BiD) | | |T7|
| |T5 | |
_________________ | T6 |_____________________
HP_DS L \______________/ \_________
| | T8 |
| T9 |
| |
HP_WRITE L_______________|______________|_______________________________
(output) | | T10 |
|T11 |
______________________ ________________________________
HP_RDY \________/
(input)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-10
MEMORY WRITE CYCLES (NORMAL MODE) 3 August 1989
+-------+-----------------------------------------------+-------+
| Name | Description | Time |
+-------+-----------------------------------------------+-------+
| T1 | SYS_CLK cycle time | 33 ns |
+-------+-----------------------------------------------+-------+
| T2 | SYS_CLK rising to HP_AS assertion (maximum) | 25 ns |
+-------+-----------------------------------------------+-------+
| T3 | Address Valid to HP_AS assertion (minimum) | 72 ns |
+-------+-----------------------------------------------+-------+
| T4 | Address Hold after HP_AS assertion (minimum) | 78 ns |
+-------+-----------------------------------------------+-------+
| T5 | SYS_CLK rising to HP_DS assertion (maximum) | 21 ns |
+-------+-----------------------------------------------+-------+
| T6 | Data setup to HP_DS deassertion (minimum) | 72 ns |
+-------+-----------------------------------------------+-------+
| T7 | Data hold after HP_DS deassertion (minimum) | 60 ns |
+-------+-----------------------------------------------+-------+
| T8 | Data Strobe deassertion time (minimum) | 226 ns|
+-------+-----------------------------------------------+-------+
| T9 | Data Strobe assertion time (minimum) | 160 ns|
+-------+-----------------------------------------------+-------+
| T10 | HP_RDY assertion to HP_DS deassertion (min) | 66 ns|
+-------+-----------------------------------------------+-------+
| T10 | HP_RDY assertion to HP_DS deassertion (max)* | 100 ns|
+-------+-----------------------------------------------+-------+
| T11 | HP_RDY assertion after HP_DS assertion | 60 ns |
| | to insure 400 ns. cycle time (max) | |
+-------+-----------------------------------------------+-------+
* If HP_RDY is asserted within the first 60 ns. of HP_DS, the
data strobe will be 160 ns. long. The timing parameter, T10,
refers to the synchronization delay if HP_RDY is NOT asserted
within the first 60 ns.
13.5 MEMORY READ CYCLES (ARBITRATING MODE)
When SWIFT wishes to begin a new transfer, it places the address of
the memory location onto the HP_DAL lines. At the same time, the
HP_ADDR16 (LOAD) signal is asserted. Three clock cycles later, HP_AS
(CTRCLK) is asserted to load the counter. Three clock cycles later,
SWIFT will withdraw the address from the multiplexed bus and deassert
LOAD. One clock tick later, SWIFT will assert HP_DS. This signals
that SWIFT wishes to read a memory location. This pulse will stay
asserted for 7 clocks. Data should be valid within 4.5 clock ticks
from the assertion of HP_DS. One clock following the deassertion of
the data strobe, SWIFT will assert HP_AS(CTRCLK) to increment the
external counter. Three clocks following the deassertion of data
strobe, SWIFT will deassert HP_AS(CTRCLK). HP_AS(CTRCLK) is thus
asserted for two clock ticks. HP_DS is deasserted for a minimum of
four clock ticks in total. For each additional contiguous word SWIFT
needs, it will assert only HP_DS and CTRCLK. If the microprocessor
wishes to access a SWIFT register while a DMA operation is in progress
EXTERNAL OPERATIONS AND TIMING Page 13-11
MEMORY READ CYCLES (ARBITRATING MODE) 3 August 1989
or an external device requests SWIFT memory bus, SWIFT will finish the
data strobe currently in progress and service the request. Following
this, SWIFT will NOT issue a new load strobe and will expect the
external logic to continue from the address which was last read.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
(input) |
| T1| | |
| |T2 | |
______ | _____|____________________________________
HP_ADDR16 |\____|_________/ |
(output) | | | |
| | | |
| | |T3 | |
| T4 | T5 | |
_____________|_____________ ______________
HP_AS _____________/ | \_______/
(output) | | | | T13 |
| | |T6
______________|_______________ ___________
HP_DS L | \______________/| |\______
| | | T12 |
| T8 | T9 | | T10 | |T7
| | | T11 | |
_____ _________ | |_______________
HP_DAL H_____< ADDRESS >_________< DATA IN >_______________
(BiD)
________________________________________________________________
HP_WRITE L
(output)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-12
MEMORY READ CYCLES (ARBITRATING MODE) 3 August 1989
+-------+-----------------------------------------------+-------+
| Name | Description | Time |
+-------+-----------------------------------------------+-------+
| T1 | SYS_CLK cycle time | 33 ns |
+-------+-----------------------------------------------+-------+
| T2 | SYS_CLK rising to HP_ADDR16 assertion (max) | 30 ns |
+-------+-----------------------------------------------+-------+
| T3 | SYS_CLK rising to HP_AS assertion (max) | 25 ns |
+-------+-----------------------------------------------+-------+
| T4 | HP_ADDR16 assertion to HP_AS assertion (min) | 85 ns |
+-------+-----------------------------------------------+-------+
| T5 | HP_ADDR16 hold after HP_AS assertion (min) | 85 ns |
+-------+-----------------------------------------------+-------+
| T6 | SYS_CLK rising to HP_DS assertion (max) | 21 ns |
+-------+-----------------------------------------------+-------+
| T7 | Data hold time after HP_DS deassertion (min) | 0 ns |
+-------+-----------------------------------------------+-------+
| T8 | Address Valid to HP_AS assertion (min) | 70 ns |
+-------+-----------------------------------------------+-------+
| T9 | Address Hold after HP_AS assertion (min) | 70 ns |
+-------+-----------------------------------------------+-------+
| T10 | Data Strobe assertion time (min) | 185 ns|
+-------+-----------------------------------------------+-------+
| T11 | Data setup time to HP_DS deassertion (min) | 65 ns |
+-------+-----------------------------------------------+-------+
| T12 | Data Strobe deassertion time (minimum) |150 ns |
+-------+-----------------------------------------------+-------+
| T13 | HP_AS deassertion time (min) |230 ns |
+-------+-----------------------------------------------+-------+
13.6 MEMORY WRITE CYCLES (ARBITRATING MODE)
When SWIFT wishes to begin a new transfer, it places the address of
the memory location onto the HP_DAL lines. At the same time,
HP_ADDR16 (LOAD) is asserted. Three clock cycles later, HP_AS
(CTRCLK) is asserted to clock the new address into the counter. Three
clock cycles later, SWIFT will withdraw the address from the
multiplexed bus and deassert LOAD. One clock tick later, SWIFT will
assert HP_DS. This signals that SWIFT has placed the data onto the
DAL lines. This pulse will last for seven clock ticks. One clock
following the deassertion of the data strobe, SWIFT will assert
HP_AS(CTRCLK) to increment the external counter. Three clocks
following the deassertion of data strobe, SWIFT will deassert
HP_AS(CTRCLK). HP_AS(CTRCLK) is thus asserted for two clock ticks.
HP_DS is deasserted for a minimum of four clock ticks in total. For
each additional contiguous word SWIFT writes, it will assert only
HP_DS and CTRCLK. If the microprocessor wishes to access a SWIFT
register while a DMA operation is in progress or an external device
requests SWIFT bus, SWIFT will finish the data cycle currently in
progress and service the request. Following this, SWIFT will NOT
issue a new load strobe and will expect the external logic to continue
from the address which was last written.
EXTERNAL OPERATIONS AND TIMING Page 13-13
MEMORY WRITE CYCLES (ARBITRATING MODE) 3 August 1989
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SYS_CLK H__| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
(input) |
| T1| | |
| |T2 | |
______ | _____|____________________________________
HP_ADDR16 |\____|_________/ |
(output) | | | |
| | | |
| | |T3 | |
| T4 | T5 | |
_____________|_____________ ______________
HP_AS _____________/ | \_______/
(output) | | | | T13 |
| | |T6
______________|_______________ ___________
HP_DS L | \______________/| |\______
| | | T12 |
| T8 | T9 | | T10 | |T7
| | | T11 | |
_____ _________ | |_______________
HP_DAL H_____< ADDRESS >_________< DATA OUT >_______________
(BiD)
HP_WRITE L______________________________________________________________
(output)
Times are as follows:
EXTERNAL OPERATIONS AND TIMING Page 13-14
MEMORY WRITE CYCLES (ARBITRATING MODE) 3 August 1989
+-------+-----------------------------------------------+-------+
| Name | Description | Time |
+-------+-----------------------------------------------+-------+
| T1 | SYS_CLK cycle time | 33 ns |
+-------+-----------------------------------------------+-------+
| T2 | SYS_CLK rising to HP_ADDR16 assertion (max) | 30 ns |
+-------+-----------------------------------------------+-------+
| T3 | SYS_CLK rising to HP_AS assertion (max) | 25 ns |
+-------+-----------------------------------------------+-------+
| T4 | HP_ADDR16 assertion to HP_AS assertion (min) | 85 ns |
+-------+-----------------------------------------------+-------+
| T5 | HP_ADDR16 hold after HP_AS assertion (min) | 85 ns |
+-------+-----------------------------------------------+-------+
| T6 | SYS_CLK rising to HP_DS assertion (max) | 21 ns |
+-------+-----------------------------------------------+-------+
| T7 | Data hold time after HP_DS deassertion (min) | 50 ns |
+-------+-----------------------------------------------+-------+
| T8 | Address Valid to HP_AS assertion (min) | 70 ns |
+-------+-----------------------------------------------+-------+
| T9 | Address Hold after HP_AS assertion (min) | 70 ns |
+-------+-----------------------------------------------+-------+
| T10 | Data Strobe assertion time (min) | 185 ns|
+-------+-----------------------------------------------+-------+
| T11 | Data setup time to HP_DS deassertion (min) | 0 ns |
+-------+-----------------------------------------------+-------+
| T12 | Data Strobe deassertion time (minimum) |150 ns |
+-------+-----------------------------------------------+-------+
| T13 | HP_AS deassertion time (min) |230 ns |
+-------+-----------------------------------------------+-------+
CHAPTER 14
MATERIAL SPECIFICATIONS
14.1 PACKAGE
SWIFT is a 68 pin Cerquad chip. Package external dimensions are
available in the SBG Standard Cell Library (Digital Semicustom
Business Group CMOS-2 Library). The package does not need a heat sink
(see the Power Consumption section).
| | | | | |
+++++++++++++
- | | -
- | | - }B
- | 68 PIN | -
- | CERQUAD | -
- | | -
- | | -
+++++++++++++
| | | | | |
|<----A---->|
|<------D------>|
A = END TO END EXCLUDING PINS = .900"
B = PIN WIDTH = .020"
C = PIN TO PIN SPACING = .050"
D = END TO END INCLUDING PINS = 1.125" +/- .005"
MATERIAL SPECIFICATIONS Page 14-2
PINOUT 3 August 1989
14.2 PINOUT
14.2.1 Signal Name To Pin Number Mapping
D
D D D D D D D D S
S S S S S S S S S
S S S S S S S S I D
I I I I I I I I - S
- - - - - - - - P S
D D D D D D D D A I
A A Q A A Q A A Q A A Q V Q R _ Q
T T V T T V T T V T T V B V I B V
A A S A A S A A S A A D I S T S S
0 1 S 2 3 S 4 5 S 6 7 D A S Y Y S
L L 1 L L 1 L L 1 L L 1 S 2 L L 1
| | | | | | | | | | | | | | | | |
+----------------------------------------+
| 9 7 5 3 1 67 65 63 61 |
| 8 6 4 2 68 66 64 62 |
| * * * * * * * * * * |
TESTOUT H --| 10 * 60 |-- DSSI_ACK L
SYSINTERRUPT L --| 11 * 59 |-- DSSI_RST L
HP_CLOCK H --| 12 * 58 |-- DSSI_SEL L
VDD --| 13 * 57 |-- DSSI_CMD L
VSS --| 14 56 |-- QVSS1
SYSCLOCK H --| 15 68 PIN CERQUAD * 55 |-- DSSI_REQ L
SYSTEST H --| 16 * 54 |-- DSSI_INPUT L
BUSGRANT L --| 17 53 |-- VSS
HPDS L --| 18 52 |-- VDD
HPAS L --| 19 51 |-- ID2 L
HPWRITE L --| 20 50 |-- ID1 L
HPADDR16 H --| 21 49 |-- ID0 L
HPDAL0 H --| 22 48 |-- SYSRESET L
HPDAL1 H --| 23 47 |-- HPCS L
HPDAL2 H --| 24 46 |-- HPRDY L
HPDAL3 H --| 25 45 |-- HPDATAEN L
IOVSS --| 26 44 |-- IOVDD
| 28 30 32 34 36 38 40 42 |
| 27 29 31 33 35 37 39 41 43 |
|________________________________________|
| | | | | | | | | | | | | | | | |
I H H H H H H V V H H H H H H H I
O P P P P P P S D P P P P P P P O
V D D D D D D S D D D D D D D A V
D A A A A A A A A A A A A D S
D L L L L L L L L L L L L D S
4 5 6 7 8 9 1 1 1 1 1 1 R
0 1 2 3 4 5 E
H H H H H H N
H H H H H H
L
MATERIAL SPECIFICATIONS Page 14-3
PINOUT 3 August 1989
14.2.2 Pin Name Mapped To IO-Cell Type
PIN NAME IO CELL TYPE DESCRIPTION
-------- ------------ -----------
DSSI_DATA<7:0> L XQBUS 86ma Open Drain XCVR
DSSI_PARITY L XQBUS 86ma Open Drain XCVR
DSSI_CMD L XQBUS 86ma Open Drain XCVR
DSSI_SEL L XQBUS 86ma Open Drain XCVR
DSSI_INPUT L XQBUS 86ma Open Drain XCVR
DSSI_REQ L XQBUS 86ma Open Drain XCVR
DSSI_ACK L XQBUS 86ma Open Drain XCVR
DSSI_BSY L XQBUS 86ma Open Drain XCVR
DSSI_RST L XQBUS 86ma Open Drain XCVR
DSSI_ID<2:0> L TLCHT TTL receiver
HP_DAL<15:00> H BD4T_R20 4ma driver,TTL receiver
HP_ADDR16 H BT4_R20 4ma driver
HP_WRITE L BD4T_R20 4ma driver,TTL receiver
HP_AS/HP_CTRCLK L BT4_R20 4ma driver
HP_DS L BT4_R20 4ma driver
HP_RDY/HP_BUSREQ L TLCHT TTL receiver
HP_BUSGRANT BT4_R20 4ma driver,TTL receiver
HP_CS L TLCHT TTL receiver
HP_ADREN L BT4_R20 4ma driver
HP_DATAEN L BT4_R20 4ma driver
HP_CLK H TLCHT TTL receiver
BUSGRANT L BT4_R20 4ma driver
SYSINTERRUPT_L BT4OD_R20 4ma open drain driver
SYSRESET_L TLCHT TTL receiver
ID<2:0>_L TLCHT TTL receiver
*SYSTEST PTP4 TEST INPUT PAD
*TESTOUT PTP3 TEST OUTPUT PAD
*NOTE: THESE ARE TEST PINS. THEY CAN BE DRIVEN/MONITORED JUST LIKE
ANY OTHER SWIFT I/O.
MATERIAL SPECIFICATIONS Page 14-4
PINOUT 3 August 1989
14.2.3 Power And Ground Pin Requirements
In general, power and ground requirements depend upon signal type and
internal gate count. For SWIFT, the Power and Ground pins required
for the different signal types are as follows:
o VSS/VDD Pins: are used to supply the I/O pad level shifters,
input pad drivers, output pad pre-drivers and internal cells.
The number recommended is one pair for every 24 pads, or one
pair for every 3000 internal gates, which ever number is
higher. SWIFT has 3 pairs of VSS/VDD pins, enough for 9000
gates and 72 pads.
o IOVSS/IOVDD Pins: are used to provide power to the pad
output drivers. The number recommended is one pair for every
twelve 4mAmp pads, including bidirectional pads. SWIFT has 2
IOVDD/IOVSS pairs, or enough for 24 output pads.
o DSSI Drivers - One QVSS1 pin is provided for every 3.1
open-drain drivers, giving a total of 5. 1 QVSS2 and 1 QVDD1
pin are also provided.
14.3 POWER CONSUMPTION
Power consumption for SWIFT was calculated at 0.693 Watts,
sufficiently low to operate without a heat sink.
Total Power = Pint + Ppadring + Pqbus
----------------------------------------------------------------------
Pint = summation(Ntype * fswitch * Fractionswitching * Ktype)
This is broken into 5 terms: one for 30 MHz logic, one for 10
MHz logic, one for the B1I's in the 30 MHZ clock line, one for the
B1I's in the 10 MHz clock line, and one for the two remaining B1I's.
Fractionswitching = 0.25 (from Hudson)
Ktypelogic = 7.0 * 10**-12 W/Hz (from Hudson)
KtypeB1I = 210 * 10**-12 W/Hz (from Hudson)
NType10MHz = 1720
Ntype30MHz = 1306
Fswitch10MHZ = 5 * 10**6 Hz
Fswitch30MHZ = 15 * 10**6 Hz
Pint = (1306 * 15*10**6 * 0.25 * 7*10**-12)W +
(1720 * 5*10**6 * 0.25 * 7*10**-12)W +
(6 * 30*10**6 * 1 * 210*10**-12)W +
(4 * 10*10**6 * 1 * 210*10**-12)W +
(2 * 5*10**6 * 0.01 * 210*10**-12)W
MATERIAL SPECIFICATIONS Page 14-5
POWER CONSUMPTION 3 August 1989
Pint = 0.09551 W
----------------------------------------------------------------------
Ppadring = Ppadinternal + Ppadexternal
Ppadinternal = summation(Ntype * ((fswitch * (K1 * Cint + K2) + K3)
* Fractionswitching + K4))
Ppadexternal = summation(Ntype * fswitch * (X1 * Cext + X2)
* Fractionswitching)
This summation is broken down into 5 terms: one internal and
one external for the 17 BD4TR20 bidirectional pads, one external for
the 8 BT4R20 output pads, one internal for the DRVT4 clock driver, and
one internal for the 8 TLCHT input pads.
fswitch = 15 MHz
Fractionswitching = 0.25 (see above)
Cint = 2 pf (estimate)
CintDRVT4 = 6.21 pf (from STATGEN)
Cext = 50 pf (estimate)
For the 4mA outputs and bidirects: (the units have been ommitted)
K1 = 0
K2 = 0.318
K3 = 0
K4 = 16.1/2 = 8.05 (This is what we were told to use)
X1 = 0.0149
X2 = 0.168
For the TTL inputs:
K1 = 0.0252
K2 = 0.050
K3 = 0
K4 = 16.1
For the Clock Driver input:
K1 = 0.263
K2 = 0.359
K3 = 0
K4 = 15.5
Ppadinternal = (17 * ((15 * (0 * 2 + .318) + 0) * .25 + 8.05)) +
(8 * ((15 * (.0252 * 2 + .050) + 0) * .25 + 16.1)) +
(1 * ((15 * (.0263 * 2 + .359) + 0) * .25 + 15.5))
= 306.0 mW
Ppadexternal = (17 * 15 * (0.0149 * 50 + 0.168)) * 0.25) +
(8 * 15 * (0.0149 * 50 + 0.168)) * 0.25)
= 85.59 mW
MATERIAL SPECIFICATIONS Page 14-6
POWER CONSUMPTION 3 August 1989
Ppadring = 0.3916 W
----------------------------------------------------------------------
Pqbus = (Idcr * VDD) + (Idcx * VDD * Nqbus)
+ (VOL * IOL * MAXlow * Dutycycle)
Idcr = 6.7 mA (From Hudson)
Idcx = 0.59 mA (From Hudson)
VOL = 0.27 V (From Hudson)
IOL = 90 mA (From Hudson)
Nqbus = 16
VDD = 5.25 V
Dutycycle = 0.5 (see above)
Pqbus = (6.7 * 5.25) + (0.59 * 5.25 * 16) + (0.27 * 90 * 10 * 0.5)
Pqbus = 0.2062 W
----------------------------------------------------------------------
Total Power = 0.693 W
CHAPTER 15
ELECTRICAL SPECIFICATIONS
Electrical Specifications for SWIFT were provided by the SBG Standard
Cell Group.
15.1 DSSI BUS ELECTRICAL SPECIFICATIONS
-----------------------------------------------------------------------
| SYMBOL | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNITS |
|-----------------------------------------------------------------------|
| Volb | Low Level | BUS Pin = 100ma; | | 0.6 | 0.9 | V |
| | Bus Voltage| Temperature=70 deg C | | | | |
| | | VDD = 4.75V | | | | |
-----------------------------------------------------------------------
| Iihb | High Level | VDD=5.25V | -50 | | 50 | uA |
| | Bus Leakage| Vin=5.25V | | | | |
| | Current | | | | | |
-----------------------------------------------------------------------
| Iilb | Low Level | VDD=5.25V | -50 | | 50 | uA |
| | Bus Leakage| Vin=0V | | | | |
| | Current | | | | | |
-----------------------------------------------------------------------
| Vihr | Bus High | VDD=4.75V; | 2.0 | | | |
| | Level Input| Temperature = 70 deg C| | | | V |
| | Voltage | | | | | |
-----------------------------------------------------------------------
| Vilr | Bus Low | VDD=4.75 | 1.2 | 1.4 | | V |
| | Level Input| Temperature = 70 deg C| | | | |
| | Voltage | | | | | |
-----------------------------------------------------------------------
15.2 NON-DSSI BUS ELECTRICAL SPECIFICATIONS
The following table was taken from the SBG SCL2 library. All tests
are specified from 4.75V to 5.25V VDD unless otherwise noted. The
ELECTRICAL SPECIFICATIONS Page 15-2
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
temperature range is 0 to 70 degrees C ambient.
HP Interface Receiver Cells:
--------------------------------------------------------------------------
Parameter Min Max Units Test Conditions
--------------------------------------------------------------------------
High Level Input Voltage 2.0 Volts VDD=4.75V
Low Level Input Voltage 0.8 Volts VDD=4.75V
Input Leakage Current -10 uAmps VDD=5.25V
Vin=0V
Input Leakage 10 uAmps VDD=5.25V
Vin=5.25V
--------------------------------------------------------------------------
--------------------------------------------------------------------------
HP Interface Driver Cells:
--------------------------------------------------------------------------
Parameter Min Max Units Test Conditions
--------------------------------------------------------------------------
High Level Output Voltage 2.4 Volts VDD=4.75V
IOH=-6MA
Low Level Output Voltage 0.4 Volts VDD=4.75V
IOL=6MA
Output Leakage Current -10 -10 uAmps VDD=5.25V
Vin=0V
Output Leakage Current 10 10 uAmps VDD=5.25V
Vin=5.25V
--------------------------------------------------------------------------
--------------------------------------------------------------------------
INDEX Page Index-1
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
INDEX
Arbitrating Mode, 11-1 Timeout Operation, 8-6
HPM bit - See CSR-HPM Bus Free Phase, 6-2
Address Counter Control, 11-2 BUS ID<2:0> bits - See ID-BUS
Memory Arbitration, 11-1 ID<2:0>
Reduced Address Capability,
11-2 checkSuM error bit - See Status
Arbitrating Mode Bit - See Word-XSM
CSR-HPM CI Overhead, 7-7
Arbitration Phase, 6-2 CI Port, 7-8
Initiator CI Port Specification, 7-2
Fair Arbitration, 9-8 ECO, 7-9
Normal Operation, 9-1 CI Specification, 7-2
Target Cirrus, 3-1
Normal Operation, 8-2 Cirrus Module, 3-1
COE bit - See DICTRL-COE
Bad Command Bytes Checksum, 8-3 Command Bytes, 7-4
Bad Command Bytes EDC, 9-4 Command Op. Code, 7-5
Bad Data Bytes EDC, 9-5 Destination Port, 7-5
Bad EDC, 9-7 Format, 7-4
Bad First Buffer bit - See Frame Length, 7-6
ISTAT-BFB Initiator
Bad Phase, 9-7 Normal Operation, 9-3
Bad Phase bit - See Status REQ/ACK Offset, 7-5
Word-BPH Source Port, 7-5
Bad Sync Character Target
First Buffer Normal Operation, 8-3
Initiator, 9-7 Command Bytes Checksum
Target, 8-5 Initiator
Nonfirst Buffer Normal Operation, 9-3
Initiator, 9-7 Target
Target, 8-6 Burn One Buffer, 8-5
BC, 12-7 Normal Operation, 8-3
BFB bit - See ISTAT-BFB Command Bytes EDC, 7-6
BPH bit - See Status Word-BPH Initiator, 9-3
Buffer Count<5:0> bits - See Command Op. Code - See Command
Status Word-Buffer Count<5:0> Bytes-Command Op. Code
Buffer Protection Command Out Phase
Buffer EDC, 10-2 Initiator
Sync Character, 10-3 Normal Operation, 9-3
Buffer Size<9:0> Bits - See Target
BUFSIZ-Buffer Size<9:0> Normal Operation, 8-1
Buffers Command out Phase, 6-2
Difference from Packets, 7-2 Command Word, 7-4
Format, 7-2 to 7-3 DEST ID, 7-4
BUFSIZ, 5-8, 7-6 Initiator
Buffer Size<9:0>, 5-8 Normal Operation, 9-2
Burn One Buffer Initiator
Buffer Count, 8-5 Normal Operation, 9-2
Normal Operation, 8-5 IOC, 7-4
Response to DSSI_RST, 8-6 Initiator
INDEX Page Index-2
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Normal Operation, 9-2 Diagnostic Mode bit - See
Target DICTRL-DIA
Normal Operation, 8-3, 8-6 DICTRL, 5-18
Target COE, 5-18
Normal Operation, 8-3, 8-6 DIA, 5-19
Configurations, 3-1 DOE, 5-18
CPR - See Current Pointer LPB, 5-19, 12-1
Register PRE, 5-19
CSR, 5-5 SRD, 5-18, 12-6
EEN, 5-5, 10-1 TST, 5-18, 12-6
HPM, 5-5 DNE bit - See Status Word-DNE
IE, 5-6 DOE bit - See DICTRL-DOE
Normal Operation, 8-6 Done bit - See Status Word-DNE
IIA, 5-6, 10-4 DSA bit - See Status Word-DSA
RST, 5-5 DSCTRL, 5-10
SLE, 5-6, 7-1 IIP, 5-11
Normal Operation, 8-2 IN, 5-10, 7-1 to 7-2
SPT, 5-5, 7-7, 7-9 Bad Sync in First Buffer, 8-5
ZF, 5-5, 7-8 to 7-9 Bad Sync Nonfirst Buffer, 8-6
Current Pointer Register Target
Initiator, 9-2 Normal Operation, 8-2
Target, 8-2 IPZ, 5-13
MI, 5-11, 7-2
Data Block, 7-6 Bad First Buffer, 8-2
Data Block EDC, 7-6, 7-8 Bad Sync in First Buffer, 8-5
Normal Operation, 9-5 Bad Sync Nonfirst Buffer, 8-6
Data Block Format, 7-6 Burn One Buffer, 8-5
Data Bytes Checksum Nonfirst buffer Bad Sync
Initiator Character, 8-4
Normal Operation, 9-5 Response to DSSI_RST, 8-6
Target Timeout Operation, 8-6
Burn One Buffer, 8-5 MO, 5-13, 7-3
Normal Operation, 8-4 Bad First Buffer, 9-2
Data Integrity Measures, 10-1 Bad Sync in First Buffer, 9-7
Data Out Phase, 6-2 Initiator
Normal Operation, 8-3 Bad Cmd. Bytes EDC, 9-4
DCS, 5-18, 12-1 Bad Data Bytes EDC, 9-5
ACK, 12-3 DSSI Reset Received, 9-8
BSY, 12-3 Error Case, 9-7
C/D, 12-3 INVALID Phase while
REQ, 12-3 expecting Command Out
DDB, 5-17, 12-1 Phase, 9-3
PTY, 12-2 INVALID Phase while
DEC Standard 161 - See CI expecting Data Out
Specification Phase, 9-4
DEST ID - See Command Word-DEST INVALID Phase while
ID expecting Status In
Destination ID - See Command Phase, 9-6
Word-DEST ID NAK Received, 9-6
Destination Port - See Command Nonfirst buffer Bad Sync
Bytes-Destination Port Character, 9-6
DIA bit - See DICTRL-DIA Read Back Error detected,
Diagnostic Control Register - See 9-8
DICTRL Selection Timeout, 9-8
INDEX Page Index-3
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Status Phase while Initiator Timeout, 9-8
expecting Command Out Target
Phase, 9-3 Response to DSSI_RST, 8-6
Status Phase while
expecting Data Out EDC
Phase, 9-4 Buffer Protection, 10-2
OIP, 5-13 Calculation, 10-2
OUT, 5-12, 7-1, 7-3 Command Bytes, 7-6
Bad Sync in First Buffer, 9-7 Data Block, 7-6, 7-8
Initiator Example C Code, 10-3
DSSI Reset Received, 9-8 Example Calculation, 10-2
Error Case, 9-7 EDC Enable Bit - See CSR-EEN
Normal Operation, 9-1 EEN bit - See CSR-EEN
Read Back Error detected, Electrical Specifications, 15-1
9-8 EPE bit - See ISTAT-EPE
Selection Timeout, 9-8 Error Protection
TPZ, 5-11 Buffers, 10-2
WP1, 5-11 DSSI, 10-1
WP2, 5-13 II Bus, 10-1
DSSI, 1-1 Registers, 10-3
Control and Status Register - External Parity Error bit - See
See DSCTRL ISTAT-EPE
Control Signals Register - See
DCS Fair Arbitration, 9-8
Data Bus Register - See DDB Frame Length - See Command
Packets - See Packets Bytes-Frame Length
Command Bytes, 7-4
Error Protection, 10-1 Goals, 1-1
ID, 4-2
Operation, 6-1 HPM Bit - See CSR-HPM
Read Back Testing, 10-1
Registers, 5-9 IAD bit - See ISTAT-IAD
Signals, 4-1 IBC bit - See ISTAT-IBC
Specification, 7-2 ID, 5-6
User Selectable Options, 7-1 BUS ID<2:0>, 5-7
DSSI Bus ID Bits - See ID-BUS P/R, 5-7
ID<2:0> Target
DSSI ID Pins vs. Register Bit - Normal Operation, 8-2
See ID-P/R IDN bit - See ISTAT-IDN
DSSI Reset IE bit - See CSR-IE
Initiator IER bit - See ISTAT-IER
Bad Cmd. Bytes EDC, 9-4 II, 1-1
Bad Data Bytes EDC, 9-5 II Bus
DSSI Reset Received, 9-8 Buffer EDC, 10-1
INVALID Phase while expecting Error Protection, 10-1
Command Out Phase, 9-3 Signals, 4-2
INVALID Phase while expecting IIA bit - See CSR-IIA
Data Out Phase, 9-4 IIP bit - See DSCTRL-IIP
INVALID Phase while expecting Illegal Register Access Detected
Status In Phase, 9-6 bit - See ISTAT-IAD
Nonfirst buffer Bad Sync ILP, 5-9, 7-1, 7-3
Character, 9-6 Bad Sync in First Buffer, 9-7
Not Enough Buffers, 9-5 Initiator
Read Back Error detected, 9-8 Error Case, 9-7
INDEX Page Index-4
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Normal Operation, 9-1 Status Phase while expecting
Successful Transfer, 9-7 Command Out Phase, 9-3
IN bit - See DSCTRL-IN Status Phase while expecting
IN Bit Cleared bit - See Data Out Phase, 9-4
ISTAT-IBC IOC, 7-4
INB bit - See ISTAT-INB ISTAT, 5-15
Inbound Buffer Error bit - See Target
ISTAT-INB Bad Cmd. Bytes Checksum, 8-3
Initiator Bad Data Bytes Checksum, 8-5
Normal Operation, 9-1 Bad First Buffer, 8-2
Initiator List Pointer - See ILP Bad Sync in First Buffer, 8-5
Initiator Pointer is Zero bit - Nonfirst buffer Bad Sync
See DSCTRL-IPZ Character, 8-4
Initiator Timeout, 9-8 Normal Operation, 8-3, 8-6
Initiator Timeout bits - See Not Enough Buffers, 8-4
TMO-Initiator Timeout Introduction, 1-1
Input Done bit - See ISTAT-IDN INVALID Phase
Input Enable Bit - See DSCTRL-IN Initiator
Input Error Bit - See ISTAT-IER While expecting Command Out
Input In Progress bit - See Phase, 9-3 to 9-4
DSCTRL-IIP While expecting Status In
Internal Loopback bit - See Phase, 9-6
DICTRL-LPB IOC - See Command Word-IOC
Internal Loopback Mode, 12-1 IPE bit - See ISTAT-IPE
Interlocks, 12-2 IPZ bit - See DSCTRL-IPZ
Read Back Error, 12-2 ISTAT, 5-15
Internal Parity Error bit - See BFB, 5-15
ISTAT-IPE Initiator
Interrupt Enable Bit - See CSR-IE Bad First Buffer, 9-2
Interrupt on Illegal Access Bit - Bad Sync in First Buffer,
See CSE-IIA 9-7
Interrupts, 7-11 Target
IE, 5-6 Bad First Buffer, 8-2
Initiator Bad Sync in First Buffer,
ACK Received, 9-6 8-5
Bad Cmd. Bytes EDC, 9-4 EPE, 5-16
Bad Data Bytes EDC, 9-5 IAD, 5-16
Bad First Buffer, 9-2 IBC, 5-16
Bad Sync in First Buffer, 9-7 Bad First Buffer, 8-2
DSSI Reset Received, 9-8 Nonfirst buffer Bad Sync
INVALID Phase while expecting Character, 8-4
Command Out Phase, 9-3 IDN, 5-15
INVALID Phase while expecting Normal Operation, 8-6
Data Out Phase, 9-4 IER, 5-15
INVALID Phase while expecting Bad Cmd. Bytes Checksum, 8-3
Status In Phase, 9-6 Bad Data Bytes Checksum, 8-5
NAK Received, 9-6 Bad First Buffer, 8-2, 9-2
Nonfirst buffer Bad Sync Nonfirst buffer Bad Sync
Character, 9-6 Character, 8-4
Normal Operation, 9-2 Not Enough Buffers, 8-4
Not Enough Buffers, 9-5 Response to DSSI_RST, 8-6
Read Back Error detected, 9-8 Timeout Operation, 8-6
Selection Timeout, 9-8 INB, 5-15
Not Enough Buffers, 8-4
INDEX Page Index-5
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
IPE, 5-16 Not Enough Buffers, 9-5
LDN, 5-17 Status Phase while expecting
Initiator Command Out Phase, 9-3
ACK Received, 9-6 Status Phase while expecting
Bad Cmd. Bytes EDC, 9-4 Data Out Phase, 9-4
Bad Data Bytes EDC, 9-5 ODN, 5-15
Bad First Buffer, 9-2 ACK Received, 9-6
DSSI Reset Received, 9-8 RST, 5-15
INVALID Phase while Initiator
expecting Command Out Bad Cmd. Bytes EDC, 9-4
Phase, 9-3 Bad Data Bytes EDC, 9-5
INVALID Phase while DSSI Reset Received, 9-8
expecting Data Out INVALID Phase while
Phase, 9-4 expecting Command Out
INVALID Phase while Phase, 9-3
expecting Status In INVALID Phase while
Phase, 9-6 expecting Data Out
NAK Received, 9-6 Phase, 9-4
Nonfirst buffer Bad Sync INVALID Phase while
Character, 9-6 expecting Status In
Not Enough Buffers, 9-5 Phase, 9-6
Read Back Error detected, Nonfirst buffer Bad Sync
9-8 Character, 9-6
Selection Timeout, 9-8 Not Enough Buffers, 9-5
Status Phase while Read Back Error detected,
expecting Command Out 9-8
Phase, 9-3 Target
Status Phase while Response to DSSI_RST, 8-6
expecting Data Out RT3, 5-16
Phase, 9-4 RTO, 5-16
Target Bad Cmd. Bytes EDC, 9-4
Bad Cmd. Bytes Checksum, Bad Data Bytes EDC, 9-5
8-3 INVALID Phase while expecting
Bad Data Bytes Checksum, Command Out Phase, 9-3
8-5 INVALID Phase while expecting
Bad First Buffer, 8-2 Data Out Phase, 9-4
Nonfirst buffer Bad Sync INVALID Phase while expecting
Character, 8-4 Status In Phase, 9-6
Normal Operation, 8-6 Nonfirst buffer Bad Sync
Not Enough Buffers, 8-4 Character, 9-6
Response to DSSI_RST, 8-6 Not Enough Buffers, 9-5
Timeout Operation, 8-6 Read Back Error detected, 9-8
OBC, 5-16 SNF, 5-17
Bad Cmd. Bytes EDC, 9-4 Initiator
Bad Data Bytes EDC, 9-5 Nonfirst buffer Bad Sync
INVALID Phase while expecting Character, 9-6
Command Out Phase, 9-3 Target
INVALID Phase while expecting Bad Sync Nonfirst Buffer,
Data Out Phase, 9-4 8-6
INVALID Phase while expecting Nonfirst buffer Bad Sync
Status In Phase, 9-6 Character, 8-4
NAK Received, 9-6
Nonfirst buffer Bad Sync LDN bit - See ISTAT-LDN
Character, 9-6 Linked Lists, 7-2
INDEX Page Index-6
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Adding to, 7-9 Output in Progress bit - See
Removing From, 7-10 DSCTRL-OIP
List Done bit - See ISTAT-LDN Overview, 2-1
Loop Back Testing, 12-1
LOTC, 12-7 P/R bit - SEE ID-P/R
LPB bit - See DICTRL-LPB Package, 14-1
Packet
MEM bit - See Status Word-MEM Data type, 7-9
Memory Error bit - See Status Length, 7-6
Word-MEM Packet Completion Modes
Memory Port - See II Bus Initiator, 9-7
MI bit - See DSCTRL-MI Target, 8-5
Microprocessor's Input Enable bit Packets
- See DSCTRL-MI Data type, 7-7
Microprocessor's Output Enable Difference from Buffers, 7-2
bit - See DSCTRL-MO Format, 7-2, 7-7
Miscellaneous Signals, 4-3 Message type, 7-7
MO bit - See DSCTRL-MO PAR bit - See Status Word-PAR
MSCP, 7-8 Parity Error
Target
NAK bit - See Status Word-NAK Burn One Buffer, 8-5
NEB bit - See Status Word-NEB Parity Error bit - See Status
No Reply bit - See Status Word-PAR
Word-NRP Phoenix, 2-1, 3-1
Non-Goals, 1-2 Pin Description, 4-1
Nonfirst Buffers Pin Types, 4-1
Initiator, 9-5 Pinout, 14-2
Target, 8-4 Port Enable bit - See DICTRL-PRE
Not ACK bit - See Status Word-NAK Power and Ground Pin Requirements,
Not Enough Buffers 14-4
Initiator, 9-5, 9-7 Power Consumption, 14-4
Target, 8-4 PRE bit - See DICTRL-PRE
Burn One Buffer, 8-5
Not Enough Buffers bit - See
Status Word NEB Read Back Error
NRP bit - See Status Word-NRP Initiator, 9-7 to 9-8
Internal Loopback Mode, 12-2
OBC bit - See ISTAT-OBC Real Data, 7-7
ODN bit - See ISTAT-ODN Register Protection
OIP bit - See DSCTRL-OIP Address separation, 10-4
OOVSIZ, 5-14, 7-9 Effects of Bad Data, 10-5
OOVSIZE<4:0>, 5-14 Error Protection, 10-3
Other Overhead Size bits - See Register Read Back, 10-4
OOVSIZ-OOVSIZ<4:0> Register Write Protect, 10-4
OUT bit - See DSCTRL-OUT Sync Characters, 10-5
OUT Bit Cleared bit - See Registers
ISTAT-OBC Address Map, 5-2 to 5-3
Output Done bit - See ISTAT-ODN Definitions, 5-5
Output Enable 1 bit - See Description, 5-1 to 5-2
DICTRL-DOE Diagnostic and Test, 5-17
Output Enable 2 bit - See DSSI, 5-9
DICTRL-COE Initialization Values, 5-20
Output Enable bit - See REQ/ACK Offset - See Command
DSCTRL-OUT Bytes REQ/ACK Offset
INDEX Page Index-7
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Reset - Originator bit - See Bad First Buffer, 8-2
ISTAT-RTO Bad Sync in First Buffer,
Reset - Third Party bit - See 8-5
ISTAT-RT3 Bad Sync Nonfirst Buffer,
Reset bit - See ISTAT-RST 8-6
Reset Command Bit - See CSR-Reset Burn One Buffer, 8-5
RFxx Disk Drives, 3-1 Nonfirst buffer Bad Sync
RST bit - See CSR-RST Character, 8-4
RST bit - See ISTAT-RST Normal Operation, 8-2
RT3 bit - See ISTAT-RT3 Not Enough Buffers, 8-4
RTO bit - See ISTAT-RTO Target
Normal Operation, 8-4
Sector, 7-8 Status Register Diagnostics Bit -
Selection Enable Bit - See See DICTRL-SRD
CSR-SLE Status Word, 7-3
Selection Phase, 6-2, 7-1 BPH, 7-13
Initiator Initiator
Normal Operation, 9-2 INVALID Phase while
Selection Timeout, 9-3 expecting Command Out
Target Phase, 9-3
Normal Operation, 8-1 INVALID Phase while
Selection Timeout, 9-3 expecting Data Out
Initiator, 9-8 Phase, 9-4
Normal Operation, 8-2 Status Phase while
Selection Timeout bits - See expecting Data Out
TMO-Selection Timeout Phase, 9-4
Signal Types, 4-1 Buffer Count<5:0>, 7-12
SII, 1-1 Initiator
SLE bit - See CSR-SLE ACK Received, 9-6
SLIM, 3-1 Bad Cmd. Bytes EDC, 9-4
SNF bit - See ISTAT-SNF Bad Data Bytes EDC, 9-5
SNF bit - See Status Word-SNF DSSI Reset Received, 9-8
Source Port - See Command INVALID Phase while
Bytes-Source Port expecting Command Out
Split Bit - See CSR-SPT Phase, 9-3
SPT bit - See CSR-SPT INVALID Phase while
SRD bit - See DICTRL-SRD expecting Data Out
Status In Phase, 6-2 Phase, 9-4
Initiator Not Enough Buffers, 9-5
ACK Received, 9-6 Read Back Error detected,
NAK Received, 9-6 9-8
Normal Operation, 9-6 Selection Timeout, 9-8
While expecting Command Out, Status Phase while
9-3 expecting Command Out
While expecting Data Out, 9-4 Phase, 9-3
NAK Status Phase while
Initiator expecting Data Out
Bad Sync in First Buffer, Phase, 9-4
9-7 Target
Target Bad Cmd. Bytes Checksum,
Bad Cmd. Bytes Checksum, 8-3
8-3 Bad Data Bytes Checksumon,
Bad Data Bytes Checksum, 8-5
8-5 Burn One Buffer, 8-5
INDEX Page Index-8
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Normal Operation, 8-6 INVALID Phase while
Not Enough Buffers, 8-4 expecting Command Out
Timeout Operation, 8-6 Phase, 9-3
DNE, 7-11 INVALID Phase while
Initiator expecting Data Out
ACK Received, 9-6 Phase, 9-4
Bad Cmd. Bytes EDC, 9-4 Not Enough Buffers, 9-5
Bad Data Bytes EDC, 9-5 Read Back Error detected,
DSSI Reset Received, 9-8 9-8
INVALID Phase while Selection Timeout, 9-8
expecting Command Out Status Phase while
Phase, 9-3 expecting Command Out
INVALID Phase while Phase, 9-3
expecting Data Out Status Phase while
Phase, 9-4 expecting Data Out
Not Enough Buffers, 9-5 Phase, 9-4
Read Back Error detected, Parity Error
9-8 Bad Sync in First Buffer,
Selection Timeout, 9-8 8-5
Status Phase while Target
expecting Command Out Bad Cmd. Bytes Checksum,
Phase, 9-3 8-3
Status Phase while Bad Data Bytes Checksum,
expecting Data Out 8-5
Phase, 9-4 Not Enough Buffers, 8-4
Target Response to DSSI_RST, 8-6
Bad Cmd. Bytes Checksum, Timeout Operation, 8-6
8-3 NEB, 7-13
Bad Data Bytes Checksum, Initiator
8-5 Not Enough Buffers, 9-5
Normal Operation, 8-6 Target
Not Enough Buffers, 8-4 Not Enough Buffers, 8-4
Timeout Operation, 8-6 NRP, 7-13
DSA, 7-13 Initiator
Target Selection Timeout, 9-8
Bad Cmd. Bytes Checksum, PAR, 7-13
8-3 SNF, 7-14
Bad Data Bytes Checksum, Target
8-5 Bad First Buffer, 8-2
Format, 7-11 XSM, 7-14
In relation to Sync Character, Bad Cmd. Bytes Checksum, 8-3
10-3 Bad Data Bytes Checksum, 8-5
Initiator Successful Transfer
Bad First Buffer, 9-2 Initiator, 9-7
MEM, 7-13 SWIFT
Initiator Configurations, 3-1
Bad Cmd. Bytes EDC, 9-4 Sync Character
Bad Data Bytes EDC, 9-5 Buffer Protection, 10-3
NAK, 7-13 First Buffer
Initiator Initiator, 9-2
Bad Cmd. Bytes EDC, 9-4 Target, 8-2
Bad Data Bytes EDC, 9-5 Nonfirst buffer
DSSI Reset Received, 9-8 Initiator
Normal Operation, 9-5
INDEX Page Index-9
NON-DSSI BUS ELECTRICAL SPECIFICATIONS 3 August 1989
Target Burn One Buffer, 8-5
Normal Operation, 8-4 Normal Operation, 8-2, 8-6
Sync Not Found bit - See Response to DSSI_RST, 8-6
ISTAT-SNF Timeout Operation, 8-6
Sync Not Found bit - See Status TMO, 5-7, 7-1
Word-SNF Initiator Timeout, 5-8
Sync Word, 7-3 Selection Timeout, 5-7
Target Timeout, 5-8
Target Command Bytes Error bit - Timeout Operation, 8-6
See Status Word-DSA TPZ bit - See DSCTRL-TPZ
Target List Pointer - See TLP TST bit - See DICTRL-TST
Target Operation, 8-1
Target Pointer is Zero bit - See User Interface, 7-1
DSCTRL-TPZ
Target Timeout, 8-6 WP1 bit - See DSCTRL-WP1
Target Timeout bits - See WP2 bit - See DSCTRL-WP2
TMO-Target Timeout Write Protect 1 bit - See
Test Bit - See DICTRL-TST DSCTRL-WP1
Test Stratagy, 12-1 Write Protect 2 bit - See
TF Tape Drives, 11-1 DSCTRL-WP2
Thread Word, 7-3
Timeouts - See TMO XSM bit - See Status Word-XSM
Timing, 13-1
TLP, 5-9, 7-1 to 7-2 Zero Fill Bit - See CSR-ZF
Bad Sync in First Buffer, 8-5 Zero-Filling, 7-8 to 7-9
Bad Sync Nonfirst Buffer, 8-6 ZF bit - See CSR-ZF