1145-KB11-KB11A
Transcribed 1/31/2019 Jay Jaeger
I do NOT guarantee 100% accuracy.
Note: In the below, PTH == "Plated Thru Hole"
Found some ECO and FCOs that may matter, but not separate rework sheets.
In reading the pamphlet that came with the DEC Maintenance Documentation Service, ECOs, those performed in house, were never released outside of the factory - instead the drawings were updated. FCOs were, and in some of those cases, below, there was detailed cut/jumper information in the DEC-O-Log. To make matters a little confusing, sometimes FCOs seems to be referred to as ECOs by later entries, but, generally, it looks like those identifiers that start with a number are ECOs and those that start with a letter are FCOs.
Below is a synopsis of what I felt was relevant. I have no way to scan the fiche. The transcriptions below are not always word for word. A (?) means I cam across something that I am not quite sure of. PTH means Plated Thru Hole
PDP-11/45
There are numerous chassis-type ECOs which I did not transcribe.
But here are some that are more "interesting" and/or may resolve safety
issues.
11/45-B0031 CODE: DF DD: C JUL-72 [FCO]
Problem 1: If plugs P12 and P13 in the PDP-11/45 power harness
are interchanged, AC is puit on the -15V EDC line.
Correction: Change AC connection on P13 to correspond to ground
pin on p12.
(more not transcribed)
11/45-B031A CODE: DF AUG-72 [FCO]
Problem: Proposed fix for potential hazard cotained in FCO
11/45-B0031 does not solve problem.
Correction: Disregard Problem 1 and Correction 1 a one wire
change ? of FCO 11/45-B0031. Disregard ADD/DELETE sheet.
(Cancels rework, becomes a documentation change only)
11/45-00037 CODE: D DD: F WL: C [ECO]
Problem: -15V and DCLO are both violet wires.
Correction: Change -15V #14 AWG grey. Change FV2 from grey
to violet.
11/45-00047 CODE: D DD: L FEB-73 [ECO]
Problem: Effectiv march 1 1973 all scheduled March and later
PDP-11/45 machiens are to have 861 power control installed in
place of 860 power control.
11/45-C0051 CODE: F WL: D APR-73 [FCO]
Problem: Fan wiring radiates AC line noise into AC LOW and
DC LOW signals in harness.
Correction: Replace 18 guage rand and white twisted pair
wiring for fans with shielded 18 guage twisted pair
#91-07701 (?)
11/45-C0052 CODE: F DD: R JUL-73 [FCO]
Problem: Top of cabinet fans inject noise into system
AC DC LO circuitry wires unless damped by H742.
Correction: Lower H742 and cabinet fans must be plugged
into line #1 of the 861 power control. Both plugs one
for the lower H742 and the other for the top cabinet fan
are to be inserted into the recptacles at the farthest
to the right when facing the 861 power control from the
front.
Symptoms exhibited before implementation of this FCO are
random failures when running the power fail diagnostic
and turning power on and off using the circuit breaker
on the 861 power control.
11/45-00053 CODE: D DD: S AUG-73 [ECO]
Problem 1: There is no warning that 15VDC is still
present when key lock is in the off position.
Correction: Add a decal.
Correction 2: Delete ?? DDP 2 software references on
drawings D AR d11 45-0-4 and C PL-11 45-0-4.
11/45-00057 CODE: D DD: Y (no date: Feb-74 to Jun-74 ?) [ECO]
Problem 1: Harness does not distribute -15V power to
system uinits when H754 (+20V, -5V) regulator is used in
CPU regulator lcoation E
Correction 1: Add connectors P45 and J45 to permit
jumpering -15V.
Problem 2: Shield for fan wiring should be grounded at
H742 to prevent noise problems.
Correction 2: Ground sheild at P23 instead of P44.
Note that H742 must have ECO H742-00019 installed.
Problem 3/Correction: Wire list as incorrect wire lenght
entries. Correct.
11/45-S0060 CODE: F DD: AB AUG-76 [FCO]
Problem: +5V power may have excessive voltage drop (greater
than 1/2 volt) to the 3-system unit options at the back of
the CPU.
Correction: Revise CPU power harness to include additional
wiring. ... Only PDP-11/45s with serial numbers below 2000
are affected.
11/45-S0061 CODE: F DD: AC JUL-75 [ECO]
Problem: machines with greater than 16K of MOS memory need
more power than can be supplied by one H746 MOS regulator.
This ECO must be installed in conjunction with ECO
KB11A-S0023.
Correction: Modify CPU harness to accommodate second H746
MOS regulator. This ECO adds P30 to the 70-9540 harness
in units with serial numbers above 2000, addes changes to old
70-08784 harness in units with serial numbers below 2000.
11/45-R0065 CODE: F DD: AH FEB-77 [FCO]
Problem 1: KB11-A backpanel must be changed for future
compatibility with FP11-C and KB11-D processor. FP11-C
will not run with KB11-A's at wire list P or earlier.
Correction 1: Update backpanel wiring. There are two
wiring DELETEs and thirty-four (ed: !!!) wiring ADDs.
Problem 2: New versions of the 11/45 using the KB11-D
must be documented. (ed. D'oh).
Correction 2: Udpate docuemntation
Rework all backpanels built after March 19, 1976. All
backpanels used in KB11-D processors must be reworked
to revision R. Retrofit all KB11-As to Wire List
revision R when FP11-C upgrade is implemented.
QUICK CHECK. Wire ADD D15E2 to F05C1.
11/45-00066 CODE: D DD: AJ JUN-76 [ECO]
Problem 1: The BM873-YB, DL11-A and the KW11-L are
being replaced by M9301-YB (for the BM873-YB) and
DL11-W (for both the DL11-A and KW11-L).
KB11 These look to be for the PDP-11/45 chassis. Only "interesting" ones
included, not the mechanical ones.
KB11-00001 CODE: D May-72 [ECO]
Problem: Etch carrying +5V current from Mate-n-Lock pins to backpanel pins
is not heaviy enough to carry required current.
Correction: Run 24AWG wire in parallel with etch on panels which already
have Mat-n-Lock assembly installed. Increase thickness of conductor with
solder bead if Mate-n-Lock assembly not installed.
PDP-11/45 system serial number 101 and later.
KB11-00002 CODE: D JUN-72 [ECO]
Problem: Two addiitional signal lines +15V, LTCL are required on KB11
system unit power distribution card.
Correction: Add additional Mat-N-Lock connector and required wiring.
KB11-S0007 CODE: F DD:Z SEP-76
Problem: Unibus routing on KB11-A backplane can cause reflections of SSYN,
BBSY and other signals due to "lumping" of A-C loads. Machine may exhibit
inexplicable problems such as parity errors, random data loss.
Correction: Reroute Unibus control signal wiring to reduce A-C loading.
Rework all KB11-A's on heavily loaded systems if symptoms are evident.
NOTES: The revision P wire list is included asn an item of documentation
as an aid in the ADD/DELETE re-routing of the KB11-A wiring. This FCO
provides excerpts from the revision N wire list showing those runs
affectedby this FCO.
QUICK CHECK; Wiring ADD a26P2 to F28D1
KB11-A CPU Backpanel
KB11A-00001 CODE: P MAY-72 [ECO]
Correction: provides minor corrections to the mounting strap drawing and
corresponding changes to the part.
KB11A-00002 CODE: M MAY-72 [ECO]
Correction: Orders reworking of card guide slots #1 and #4.
KB11A-00003 MAY-72 [ECO]
This ECO replaces and supersedes ECO 7008871-00002
KB11A-00004 MAY-72 [ECO]
This ECO replaces and supersedes ECO 7008871-00003
KB11A-00005 CODE: M JUN-72
Add a rubber bumper to prevent scratching of decal on fan housing
KB11A-A0008 CODE: DF DD: C WL:D JUn-72 [FCO]
Problem: CMP.B and BIT.B instructions with R7 as a destination
cause PC to be modified when source is a general register.
Correction: Add signal BACB UPWEOO from GRA to DAP modules
KB11A-00007 CODE: P DD: D AUG-72 [ECO]
Correction: Adds information missing from drawing E-MU-KB11-A-01
Documentation change only.
KB11A-B0008 CODE: DF DD: E WL: E SEP-72 [FCO]
Problem: Small peripheral controller slots in KB11-A panel, slots
26 thru 28, are not wired to accept some quad module controlers:
NPG, PA, PB, LTC, ACLO, DCLO and +15V are missing.
Correction: Revis wiring to include signals lsited above.
KB11A-B0009 CODE: F DD: F WL: F [FCO]
Problem: Signal required for use on M8109 timing generator not
presently wired on backplane.
Correction: Bring ROM 40 BL signal from RACB to TIGA. Add
wire to backplane D09J1 to C15M1. This FCO must be installed in
conjunction with M8109-B0008
KB11A-00010 CODE: D SEP-72 [ECO]
Problem: AC wiring being pinched during opening and closing of
cover of top fan housing.
Correction; Use only IMC BOXER fans on assembly #12-05033-1
KB11A-00011 CODE: P DD: H WL: H NOV-72 [ECO]
Correction: Change KB11-A Wire List prefixes to agree with prefixes
in print set. Documentation change only.
KB11A-A0012 CODE: F DD: J WL: J DEC-72 [FCO]
Problem: 11/45 processor does not meet UNIBUS cycle time specification.
Correction: Correct KB11-A back panel attached ADD/DELETE sheet and
install FCO M8106-A0005 to UBC module.
NOTE: See correctino supplement FCO KB11A-A012A
NOTE: FCO M8106-A0005 is a prerequisite to this FCO.
KB11A-A012A CODE: F DEC-72 [FCO]
Problem: Not all the add/deletes listed on sheet 2 of KB11A-A0012
are necessary for this retrofit.
Correction: use the ADD/DELETE sheet included in this supplement
for FCO KB11A-A0012.
KB11A-E0013 CODE: F DD: K WL: K JAN-73 [FCO]
Problem: Improvie performance of PDP-11/45 processor as UNIBUS
master.
Correction: Revise KB11-A Wire List as defined the ADD/DELETE
sheet and install etch revision C M8104 module
NOTE: This FCO completes the total FCO package necessary
for improving the speed performance of the PDP-11/45 with
core memory. Note prerequisite FCOs are KB11A-A0012,
KB11A-A012A and M8106-A0005.
KB11A-00014 CODE: P DD: L [ECO] JAN-73
Correction: Correct errors on the KB11-A Flow diagram drwing.
DD-FD-KB11-A-03. Documentation change only.
KB11A-D0015 CODE: F DD:M WL:L [FCO] MAR-73
Problem: Detection of parity errors through vector 4 is slow.
Correction: Detect parity errors through vector 114.
Wire Adds:
D11D2 to A06P1, E12A1 to F11F1, C09K1 to E12A1
NOTE: This FCO must be installed in conjunction with the following
FCOs to implement *core* parity: M8100-D0003,
M8103-D0005, M8106-D0007 and M8106-D0008. Each of thsee related
FCOs may be installed separately.
Note that MS11-B/-C semiconductor parity memories with etch
revision B M8110s will NOT function properly when above FCOs
are installed. A new M8110 is being designed to function with
these FCOs
KB11A-00016 CODE: P DD:N WL:M MAR-73 [ECO]
Problem: KB11-A Wire List changes on previous ECOs were not
documented correctly in Wire List revisions.
Correction: Back the following wire list documentation
changes: Signal names BUSA ACO L and RACB UPWE00 H pins
to be added, C28V1 and E06V2.
KB11A-0016A CODE: P JUN-73 [ECO]
Problem: The ADD/DELETE sheet distributed with ECO
KB11A-00016 was distributed in error.
Correction: Disregard the ADD/DELETE sheet. Correction
notation on ECO KB11A-00016 contains sufficient informatino.
KB11A-B0017 CODE: F DD: P W: N MAY-73 [FCO]
Problem: The KT11-C fails to abort on internal references.
Marginal timing condition contributes to unreliable system
performance.
Correction: Add more precising timing to the M8108 modules
by substituting T for TP signal. The M8108 module must be
at CS revision F or later.
KB11A-B017A CODE: F JUN-73 [FCO]
Problem ADD/DELETE sheet on FCO KB11A-B0017 is too difficult
to install. BREAK-IN EFFECTIVITY is no longer appropriate.
Correction: Disregard ADD/DELETE sheet on FCO KB11A-B0017
and install ADD/DELETE sheet included with this supplement
instead. The ADD/DELETEs are as follows:
ADD C15S2 to E13A1 and C15R1 to E11C2, a twistedpari.
Disregard BREAK-IN EFFECTIVITY on FCO KB11A-B0017.
All KB11-A panels manufactuired after 6/18/73 must included this
change. Also, all KB11-A panels with the KT11-C installed and with
the M8108 having FCO M8108-80007 installed must have this change.
KB11A-00018 CODE: P DD:R AUG-73 [ECO]
Problem: Duplicated effort is being expended in wrapping the two
signals SMCE MEM D14 H and MSCE MEM D15 H
Correction: Delete SMCE MEM D14 H and SMCE MEM D 15 H from the
wired assembly drawing as these two signals are presently being
wrapped by the wire list. Documentation change only.
KB11A-00019 CODE: P DD: S DEC-73 [ECO]
Problem: Two versions of the M8109 are bing shipped, but only one
Circuit Schematic drawing is part of the print set.
Correction: Include both the standard and special revision drawings
in all print sets by listing the special M revision on drawing
B-DD-KB11-0
KB11A-00020 CODE: P DD: T JUN-74 [ECO]
Problem: Screw #90-09041-2 si not long enough to reach int soacer.
Correction: Replace with longer screw, nylon, 90-08212-1.
KB11A-00021 CODE: M DD: U JUN-74 [ECO]
Present frame for the 11/45 CPU is expensive and it is difficult to
maintain specifications.
Correction: Replace frame with a die cast frame.
KB11A-00022 CODE: M DD: V JAN-75 [ECO]
Problem: Die cast frame 74-10882 which was expected to be implemented
January 1 1975 is not coming in from vendor correctly: some serious
design problems have also materialized.
Correction: Cotninue to use old assembly and related parts and do
not phase-in die cast frame 74-10882 that was called out on ECO
KB11A-00021.
KB11A-S0023 CODE: F DD: W JUL-75 [FCO]
Problem: machines with over 16K of MOS memory need second H746
regulator and require CPU backplane rework.
Correction: Rework assembled KB11-A backplanes. Modify CPU
harness to accommodate second H746 MOS regulator. This ECO adds
P30 to the70-09540 harness in units above serial number 2000.
Add changes to the old70-8784 harness in units below serial
number 2000.
NOTE: The field implementation details for FCO 11/45-00061 were
incorporated into this FCO to facilitate its coincident
implementation.
QUICK CHECK: H746 added in slot L of lower H742.
KB11A-R0024 CODE: F DD: Y NOV-75 [FCO]
Symptom: Bipolar memory loses power to do etch failure.
Problem: Excessive voltage drop across +5V etch running to
semi-conductor memory locations slots 16 through 25.
Correction: Add five wires (#18 AWG Red) from Mate-N-Lock
pin (soldered end of pins) to semi-conductor memory
locations.
QUICK CHECK: Wires added at A16A2, A19A2, A21A1, A24A2 and
A02A2 (sic).
M8100-00001 CODE: D CS A Etch A APR-72
Problem: Incorrect Range for START VECTOR
Correction: Change Etch, correct print errors
M8100-0001A CODE: D MAY-72
Correct Error in M8100-00001
Correction: Correct assembly hole drawing to show a jumper from
E11 pin 12 to E36 pin 4
M8100-A0002 CODE: DF CS B Etch B JUN-72 [FCO]
Relayout board to eliminate jumpers and etch cuts
NOTE: Info for M8100-0004 indicates that no Etch B made it
into the field.
M8100-A002A CODE: DF JUN-72 [FCO]
Problem: Disposition code on M8100-A0002 is 02: phase-in
Correction: Change to code 03: rework immediately.
Problem: CMP.B and BIT.B instructions with 8MO (?) and DMO (?)
DF7 will destroy the PC
Correction: Inhibit PCB clock under those conditions
M8100-C0003 CODE: F CS C Etch C JAN-73 [FCO]
Problem 1: Parity errors require the generation of trap vector 114
Correction: Modify Trap Vector logic
Required on all 11/45 systems with parity
Problem 2/Correction 2: Correct print errors on sheet copy
M8100-C003A CODE: F [FCO]
Change disposition code to 03 (allow rework)
M8100-00004 CODE: D CS D MAR-73 [ECO]
M8100 generates a jumper selectable power-up vector address of
either octal 000024 or 173224 for 11/45,50,55 CPUs. M9301
boostraps require a vector of 173024 for push button boot and
always boot after power fail functions to work when memory
locations 0-4K are semiconductor memory
Correction: Modify M8100 to permit separate jumper selectable
assertion of bit 07 and vector extension selectable
as either 000XXX or 173XXX by adding an additional jumper (W7)
(Prior to this ECO, selection of bit 07 [ed. so probably 07 is
what got smudged, above) automatically asserted the 173XXX
vector extension)
Phased in to all modules built after July 4, 1976.
M8100-R0005 CODE: F CS: D Etch: D JAN-77 (yes, 1977) [FCO?]
Correction 1: correct module history to rflect ECO's 00003
and 0003A
Problem 2: ECO M8100-0004 is incomplete because additional
modifications are needed for etch revision A M8100s which were not
included.
Correction 2: Add step to procedure to include revision A.
Problem 3: ECO M8100-00004 the procedure may be confusing because
it lacks a clear description of IC socket
Correction: Refer to this ECO for diagram describing socket E26
QUICK CHECK: Wire ADD from E18 pin 12 to E25 pin 6 (that is just a
check, not the entire change!)
M8101-00001 CODE: D CS B MAR-72 [ECO]
Unavailability of 74S194 ICs
Use 74194 ICs
M8101-00002 CODE: P JUN-72 [ECO]
Correct Schematics (documentation only)
M8101-B0003 CODE: F CS D DEC-72 [FCO]
74194-1 ICs not available
Change part description to 74S194
Problem 2: IC E62 is too slow under worst case conditions
Replace E62 74194/74194-1 with 74S194
M8103-00001 CODE: D CS B Etch C MAY-72 [ECO]
Relayout to eliminate jumpers and etch cuts
M8103-B0002 CODE: DF JUL-72 [FCO]
Problem: Address Lines change between BUST-BEND cycles during
SOB, MARK, and FP instructions causing data in MOS memory to be
altered
Correction: Change ROM code for those instructions to keep address
lines from changing.
M8103-00003 CODE: D CS D JAN-73 [ECO]
Selected Schottky parts no longer needed
replace 74S153-1 and 74S64-1 with 74S153 and 74S64
M8103-D0004 CODE: F CS E JAN-73 [FCO]
Problem: Signal RACB UBSD01 H is overloaded and RACB ROM40 B L
causes bad T3 pulses under margins
Correction: Buffer UBSD01 and bring to same module finger as ROM40 B
Note: Without this FCO, proper operation of the PDP-11/45 cannot be
guaranteed with the processor operating at approximately 250 to 280
nsec. T1 to T1.
M8103-C0005 CODE: F CS F MAR-73 [FCO]
Problem: parity errors need special abort logic to assert
ZAP signal.
Correction: Modify ZAP gate on RACA
(There is an M8103-C005A, which is just a cover sheet change)
M8103-C0006 CODE: F CS H OCT-73 (CO-requisite M8105-C0007) [FCO]
Problem: The processor can hang in T2 and pause with
UBCB GET BUS flip flop cleared because of a glitch on the
RACH DIS BUS T signal. In MOS or bipolar memory systems
data may be taken from the wrong address.
CORRECTION:
Change RACH DIS BUST L to RACH BUST H
Cut etch side 2 from E54 pin 9 to feed thru
Jumper: E40 pin 2 to E17 pin 1
E40 pin 12 to E54 pin 9
E40 pin 1 to E94 pin 7
E40 pin 13 to feed thru at lower right of
E86 pin 8 which connects on side 2 to DU2
M8105-00001 CODE: D CS B Etch C MAR-72 [ECO]
Etch Errors
M8105-00002 CODE: D CS C MAY-72 [ECO]
Change disable gate in priority arbitration
M8105-B0003 CODE: DF CS D Etch E Aug-72 [FCO]
Problem: PIRQ LEV 1 request locks out T bit if PSW priority is
at LEV 1
Correction: remove PIR LEV 1 from inhibiting T bit by
Cutting etch from E50 pin 5 to E46 pin 6
Adding jumper from E50 pin 5 to E50 pin 4
NOTE: Existing diagnostics (at the time) did not test for this
M8105-00004 CODE: D CS E DEC-72 [ECO]
Not necessary to have 74S74-45 in E37
Replace with 74S74
M8105-D0005 CODE: F CS F MAR-73 [FCO]
Parity errors are time consuming to detect through vector 4
Core parity requires these changes:
M8100-D0003, M8103-D0005, M8105-D0005, M8106-D0007,
KB11A-D0015 and M8106-D0008
FCO's may be installed separately - each FCO relies upon the others
only to fully implement parity.
NOTE: MS11-B/-C semiconductor parity memories with etch revision
"B" M8110s will NOT function properly with these FCOs.
A new M8110 was designed)
M8105-C0006 CODE: F CS H JUN-73 [FCO]
Problem: references to internal registers cause unnecessary data
to be put on the UNIBUS
Correction: Disable TMCD XX BYTE EN H until master sync is asserted
Cut:
E15 pin 2 side 2
Third plated thru hole (PTH) left of E05 pin 1 side 1
Jumper:
PTH connected to E09 pin 7 to PTH to right of E09 pin 7
PTH connected to E09 pin 1 to E16 pin 2
PTH connected to E09 pin 2 to E07 pin 2
E15 pin 2 to E15 pin 5
PTH connected to E09 pin 3 to third PTH left of E01-05 ****
CAREFUL: Note the DISCREPANCY with 2nd cut. ?????
One of the two is probably WRONG. ??? ****
INSERT: 74S00 at E09
M8105-C0007 CODE: F CS J OCT-73 [FCO]
(See M8103-C0006 for description)
Co-requisite M8103-C00006
Correction: Create ROM decode of BUST H on the M8103 board.
Jumper the new source of BUST H into M8105 logic.
On THIS board (M8105)
Cut: E34 pin 08 side 1
Jumper: PTH CT2 to PTH DU2
M8105-0008 CODE: D CS K Etch E NOV-73 [ECO]
MOS Memory Systems with KT11-C could pick up bits [Ed. I think they
mean pick up as in cause bits to flip ON] in MOS Memory during
KT11-C abort traps.
Correction: Issue TMCE BEND CLRL to MOS control during the pause
ROM cycle.
No rework! They issued a new Etch F
M8106-00001 CODE: D CS B APR-72 [ECO]
Problem 1: UBCE (?) PUT flipflop gets cleared after DCLO
goes away by START SW because 15V is not present at the console
when DCLO becomes false.
Correction 1: Remove START SW from clearing PUP and replace with
UBCB ABORT ACKN L.
Problem 2: TIG signal prefixes change due to additional
TIG print
Correction 2: Correct TIG names
Problem 3: Clearing SEG ABORT with ACKN is not fast enough for
operation at 140 nsec
Correction 3: remove SEG ABORT from SSYN RESTART and use
ABORT * DESKEW COMPLETE to restart. Also remove BUST * T2
from clearing DESKEW register.
M8106-B0002: CODE DF CS: C MAY-72 [FCO]
Timing DFiagram must gbe added to print set. Etch board ready
to be corrected.
Add Timing Diagrams UBCK, UBCL and UBCM to prints.
relayout etch as per revised assembly hole drawing.
M8106-B002A CODE: DF MAY-72 [FCO]
Problem 1/Correction 1: Original ECO (sic) has incorrect disposition code.
Problem 2: Power fail with yellow stack has marginal timing when
running in bipolar memory.
Correction 2: change timing to set UBCE CLR PF at leading rather
than trailing edge of TS3.
M8106-C0003 CODE: F CS: D AUG-72 [FCO]
Problem 1: TIME OUT needs to be lengthened on certain systems.
Correction 1: Add chart for TIME OUT capacitors to print set.
Problem 2: Some options need to use BUS PARITY lines
Correction 2: Add jumper to disable parity check on UNIBUS
NOTE: See correction supplement FCO M8106-D0007 which cancels
the creation of a new etch revision "D" as ordered by this FCO.
M8106-00004 CODE: D CS: E DEC-72 [ECO]
It is not necessary to use 74S74-45 IC's for E75
Replace E75 with 74S74's
M8106-A0005 CODE: F CS: F DEC-72 [FCO]
Problem: Present board not meeting cycle time specifications for
UNIBUS.
Correction: Add logic changes.
NOTE: This FCO must be installed in conjunction with FCO
KB11A-A0012
NOTE: This FCO is a prerequisite for the use of a new etch revision
C M8104 which will be released.
NOTE: See correction supplement FCO's M8106-A005A and M8106-A005B
NOTE: Supplement FCO M8106-A005B cancels the relayout to new
etch revision "E" which was ordered by this FCO.
M8106-A005A CODE: F JAN-73 [FCO]
Problem 1: Rework procedure in M8106-A0005 is incorrect.
Correction 1:
In step #2 changed E83-11 to E83-13
In step #4 change R23 to R22
Problem 2: The assembly hole drawing does not specify which
side of the board etch cut #13 is on
Correction 2: Side 2
M8106-A005B CODE F APR-73 [FCO]
Correction: Cancel relayout of etch board as ordered by FCO M8106-A0005
M8106-D0006 CODE F CS: H FEB-73 [FCO]
Correction: Add print changes required to document FCO KB11A-E0013.
Add prints UBCN and UBCP
M8106-D0007 CODE: F CS: J [FCO]
Problem: Parity errors are time consuming to detect through vector 4
Correction Allow processor to trap to 114 for parity errors.
This FCO indicates that the etch revision D boards ordered by
FCO M8106-C0003 will not be built.
(See M8105-D0005 for more info)
M8106-D0008 CODE: F CS: K MAR-73 [FCO]
Problem: UNIBUS parity errors cause machine to halt
Correction: Disable UBCB UNI PERF [ 1 ] L from
generating UBCB PARITY ERR SET L.
(Also see M8105-D0005 for more info)
M8106-00009 CODE: D MAR-73 [ECO]
Problem: Manufacturing costs are high to build board
Correction 1: Relayout board
Correction 2: Remove UBCB PARITY ERR INH L from E82 pin 12
NOTE: This ECO is cancelled by supplement ECO M8106-0009A
NOTE: CS Revision L and etch revision F created by this ECO are
cancelled by supplement M8106-0009A
M8106-0009A CODE: D MAY-73 [ECO]
Problem: More changes are required to revision F etch board
Correction: Cancel ECO M8106-00009 and return drawings to
previous revision levels
M8106-00010 CODE: D MAY-73 [ECO]
Problem: The processor randomly halts when MOS parity memory
has HALT ENABLE set
Correction: Strobe SMCB PE HALT L at the trailing edge of
CONTROL OK.
NOTE: This ECO is cancelled by supplement ECO M8106-0010A
NOTE: CS Revision L which si created by this ECO is cancelled
by M8106-0010A.
M8106-0010A CODE: D MAY73 [ECO]
Cancel M8106-00010 More problems have occurred
M8106-C0011 CODE: F CS: L MAY-73 [FCO]
Problem: CONSOLE START function or RESET INSTRUCTION could cause
machine to hang.
Correction: Asssert UBCE RIP OR FP SYNC L faster to ensure branch
condition.
CUT: Etch from E32 pin 3 to E32 pin 4 side 2
Etch from E32 pin 4 to PTH side 2
Jumpers: Second PTH left of E32 pin 2 to PTH below E22 pin 2
E32 pin 4 to E38 pin 4
M8106-C0012 CODE: F CS: M JUN-73 [FCO]
Problem: MOS Parity memory is too tight.
Correction: Strobe parity errors sooner
NOTE: See M8106-C0012A
Rework in parity systems with M7259 or etch revision C M8110s,
rework all systems with parity and all PDP11-45s at next PM.
M8106-C0012A CODE: F JUN-73 [FCO]
The rework procedure in M8106-C0012 in steps #25 and #26
incorrectly references an R22. Should be R20.
M8106-00013 CODE: D CS: N ETCH F AUG-73 [ECO]
Problem: Multiple parity errors from CONSOLE MODE can cause
machine to HANG.
Correction: Relayout board to remove UBCB PARITY ERROR INH from
E82 pin 12.
NOTE: No etch revisions C, D or E have been built.
M8106-C0014 CODE: F MAR-74 [FCO]
Problem: Processor could possibly hang during a BR sequence
with a CS revision M M8106 as a result of a missint +3V signal.
Correction:
Jumper direct set and D input of UBCA PASSIVE flipflop to UBCA +3V H.
Jumper E063 Pin 10 to E054 Pin 08
M8106-D0015 CODE: F CS: P JUN-74 [FCO]
(Hard to read)
Problem: A power fail sequence does not work when in Console Lock
mode because the CONSOLE START LATCH flipflop on the console may
come up set.
Correction: Gate UBCR START 1 H to UBCE STATUS CLR L on the
M8106 board.
Cuts:
Both etch runs on side 2 at E31 pin 2
Jumper:
PTH beside E31 pin 1 to PTH directly below E02 pin 3 (?)
E31 pin 2 to E5 pin 5
M8106-S0016 CODE: F CS: R DEC-75 [FCO]
Problem: Excessive interrupt to vector skew can cause improperly
clocked-in vectors (this results in vectoring to random locations)
Correction: Add 125 nsec delay to deskew Bus Interrupt.
The rework is extensive and the followin components are added:
one each 13-00250 a 150 ohm resistor
13-00271 a 220 ohme resistor
10-05820 a 22 pfd capcitor
16-11300, a 125 nsec delay line
NOTE: Rework only as necessary.
M8106-S0017 CODE: F CS: S MAR-77 [FCO]
Problem: A halted PDP-11/45 on (sic - s/b or) PDP-11/50 CPU can not be
restarted by just assering Bus ACLO (for new Down Line Loading feature).
Correction: Add logic to restart halted CPU (halt switch up) when ACLO
is asserted on the Unibus.
QUICK CHECK: Wires added from E24 pin 4, 5 and 6
M8106-00018 CODE: D CS: T SEP-79 [FCO]
Problem: Direct set signal to CPBSY flipflop is not of adequate duration
to insure proper operation, causing unexpected reads of location zero.
Correction: inhibit assertion of signal BUSA MSYN if CPBSY resets during
deskew.
M8107-B0001 CODE: DF CS: A May-72 [FCO]
Problem: Etched board has etch cuts and jumpers.
M8107-B001A CODE: DF JUN-72 [FCO]
Problem: FCO M8107-B0001 incorrect. Must also retrofit each rev A board
to make actual circuit identical to schematic.
Correction: TO A etch revision board ONLY
Jumper: E71 pin 3 to E80 pin 1
Connects SAPL +3VA to E71 pin 3
M8108-00001 CODE: D CS: A APR-72 [ECO]
Problem 1: Wrong Termination
Correction 1: Eliminate resistor R2, change R1 to 150 ohms
Problem 2: Race condiation at 1.2 usec ROM cycle
Correction 2: Synchronize inhibit signal with flipflop on SSRK.
Problem 3: No error flipfop not setting
Correction 3: Clock register SRO earlier
Correction 4: Drawings changed to correct print errors
Problem 5: TIG Changes
Correction 5: Change prints
Problem 6: Hole in Execute only space
Correction 6: Change I space logic -SSRB
M8108-00002 CODE: D CS: B APR 72 [ECO]
Problem: An MTPI instruction when D space is enabled and current
and previous modes are both user will not write into the D space
if D space is write-enabled
Correction: Under the above circumstances, allow MTPI to try to
write in I space. This is OK since I space will normally be
read only when set up as an EXECUTE ONLY situation hence the MTPI
will be aborted. Signal SSRJ C1 B L determines whether it is
MTPI or MFPI.
NOTE: See correction supplement M8108-00003
M8108-00003 CODE: D CS: C APR-72 [ECO]
Correction 1: Corrects note on ECO M8108-00002
Problem 2: On a KT11-C abort, using console physical for an examine
sometimes gave an address error on trying to examine KT11-C registers.
Correction 2: Clear inhibit signal with the fact that the access is
a console physical operation.
M8108-B0004 CODE: DF CS: D Etch: B APR-72 [FCO]
Problem: Etched board has etch cuts and jumpers from ECOs M8108-00001
through M8108-00003.
Correctino: Corrrect etched board to reflect revision C Circuit Schematic.
NOTE: See correction supplement FCO M8108-A004A (sic)
Rework all etch revision A M8108's.
M8108-B004A CODE: DF JUN-72
Problem: FCO M8018-B0004 incorrect. Must also retrofit etch revision A
boards to make actual circuit identical to schematic.
Correction: To A etch revision boards only:
Jumper: E85 pin 4 to PTH below pin 1 on E107
Connects signal SSRL INT CLRA L to E85 pin 4. Also update CS revision D.
NOTE: Attempt to access any supervisor page address register with the
KT11-C enabled may cause the processor to hang.
M8108-00006 CODE: P CS: E MAR-73
ECO M8108-00005 was cancelled by supplement ECO M8108-0005A
Problem: Circuit Schematic drawing showing etch revisiion B still says
"Etch Revision A".
Correction: Change each letter on Circuit Schematic drawing to B.
Update module history and assembly hole drawing.
M8108-B0007 CODE: F CS: F MAY-73
Problem: Fails to abort when illegal address is internal register.
SSRK inhibit 1 L fails to block TIGD T5BH on SSRL D-S.
Correction: On SSRK replace signal SSRK TS4 H with
TIGC T4BH at E79 pin 13.
NOTE: The KB11-A must be at WL revision N or later. Reference
FCO KB11A-B0017
All etch revision A and revision B M8108's must be reworked.
KB11-A must also be reworked.
M8109-00001 CODE: D CS: C [ECO] APR-72
Problem: Synchronizer for T1 will not work when T1 SYNC flipflop
is used for logic gating.
Correction: Remove all logic gating responsiblities except for T1 and
T1A (?) from T1 SYNC . Clear T1 SYNC and T5 flipflop with
T1 [ 1 ] L.
M8109-00002 CODE: D CS: D [ECO] MAY-72
Correction: Changes the 22 Uf capacitor to fit flush on the board
where components are mounted close together.
M8109-A0003 CODE: DF CS: D [FCO] JUN-72
Problem: Part change. 11/45 timing generator M8109 adjustment
at 150 nsec range difficult with present value of R162 in RC
oscillator circuit.
Correction: Change value of R162 to 1K 1/4W 10% to facilitate adjustment.
M8109-A0004 CODE: DF CS: F JUN-72 [FCO]
Problem: 11/45 processor skips ROM cycles
Correction: Modify STOP T3 (?) logic for ROM and UPB conditions by
disabling STOP T3 (?) with CONTINUE [ 1 ] clearing associated
syncrhonizing flipflp with T5 (?) [ 1 ] L
(ed. Had to tell 3's from 5's)
M8109-00005 CODE: D CS: H Etch: D JUN-72 [ECO]
Problem: General clean up of M8109 timing generator.
Correction: Partial relayout of M8109 to minimize the use of jumper
wiring and to update logic.
M8109-A0006 CODE: DF CS: J JUN-72 [FCO]
Problem: Fast memory is modified or machine traps out when
KT11 option segmentation is installed. This is caused by SSR DLY
flipflop oscillating when SSRB ENABLE T3 DLY timing violates set up
or hold times.
Correction: Move SSRB ENABLE T3 DLY directly to TIGA STOP T3 L
multiplexor and modify SSR DLY flipflop to control only the
delay time.
MAINDEC T15 diag. GTP also changed.
M8109-00007 CODE: D JUN-72 [ECO] JUN-72
Problem: Tuning slug protrudes from inductor housing at final position
Correction: To improve tuning slug adjustment and final positioning
change the value of C154 from 100 pf to 82 pf
M8109-0007A CODE: D [ECO] JUL-72
Problem: Part change called for in ECO M8109-00007 does not work.
Correction: Rescind ECO M8109-00007 and reactivate documents at
revision level J.
M8109-B0008 CODE: F CS: K Etch E [FCO] SEP-72
Problem: The T3 flipflop forced to synchronize because of UBSD 00 (?)
and UBSD 01 (?) logic delays
Correction: Bring ROM 40 BL signal from RACB to TIGA C15M1. add inverter
on TIGA make necessary etch cuts and jumpers.
(ed. This has KB11A-B0009 as a pre-req.)
M8109-00009 CODE: D CS: L [ECO] OCT-72
Problem: Documentation correction. Bypass cpacitor C80 (?) is not shown
connected to ground on etch.
Correction: Update prints and add jumper from C80 top to ground above Q10.
(ed. This could aos be C60 - hard to read)
M8109-00010 CODE: D CS: M DEC-72 [ECO]
Problem: It is not necessary to ahve 74S76-45 DEC ICs for E8 and E34.
Correction: Change part numbers for E8 and E34 from 74S76-45 DEC
#19-10950 to 74S74 DEC #19-10544.
M8109-00011 CODE: D CS: N ETCH: F [ECO] JAN-73
Correction: Orders partial relayout to eliminate jumper wiring and to update
the logic.
M8109-00012 CODE: D CS: M1 [ECO] FEB-73
Problem: The 74S74-45 E15 may not operate well as a synchronizer in this
circuit.
Correction: Change E15 from 74S75-45 DEC #19-10950 to 74S74-50 DEC
#19-11326
M8109-C0013 CODE: F CS: M2 DEC-73 [FCO]
Problem: High speed synchronizer chip 74S74-50 #19-11326 is not available
in sufficient quantities to satisfy production.
Correction: Change logic from single to dual synchronization configuration.
Procedure:
Check to see if E08 is 74S74-45 #19-10950. The "45" is usually stamped in
yellow. If it is, proceed with etch cutting and jumpering. If it is not,
remove E08 74S74 #19-10544 replace E08 with 74S74-45 #19-10950.
If the M8109 has a jumper from E07 pin 10 to E08 pin 4 be sure to put it in
place when replacing E08. Do all etch cutting and jumperi9ng which follows
before soldering E08 in place.
Cut: Etch from side 1 at PTH above E13 pin 8
Etch fomr side 2 at pin 9 of E21
Jumper: From top of R151 to E8 pin 12
E8 pin 11 to E8 pin 3
E8 pin 13 to E8 pin 1
E8 pin 9 to E13 pin 6
E8 pin 10 to E15 pin 1
(ed. the print is really small and numbers hard to read)
NOTE: If the system has bipolar memory, the M8110 must be replaced by an
M8120.
All etch revision C boards inproduction not having E15 as a 74S74-50
DEC #19-11326 must be reworked immediately.
M8109-00014 CODE: D CS: P FEB-74 [ECO]
Problem: Etch Error. The signal TIGB SSR MAT H is grounded.
Correction: Cut etch and add jumper to bypass ground.
Cut: Etch from E3 pin 6 on side 2
Etch from PTH above pin EL2 on side 2
Jumper: PTH on pil EL1 to E3 pin 6
M8019-C0015 CODE: F CS: R CS: M3 APR-74 [FCO]
Problem: CPU fails to halt on selected ROM state when
Micro Program break mode is set on maintenance card. The problem
is detected when running a test sequence not containing a pause
150 nsec cycle time.
Correction: Delete U/L: CTRL latch flipflop and add latch at input
gating. Test by running a branch dot with ROM match at 343.
FOR ETCH REVISION C:
Cuts:
Side 2 at E12 pin 9
Side 2 E32 pin 9 to E31 pin 13
Side 2 E32 pin 9 to E32 pin 10
Side 2 at E42 pin 13
Remove jumper E22 pin 14 to E35 pin 7
Jumpers:
E12 pin 9 to E22 pin 11
E42 pin 13 to E35 pin 7
E42 pin 8 to E32 pin 9
E32 pin 10 to E31 pin 13
FOR ETCH REVISION F:
Cuts:
Side 2 from E12 poin 9
Side 2 E40 pin 9 to E40 pin 10
From PTH on right side of pin 7 of E40 side 1
Side 2 from E26 pin 13 two runs.
Side 2 from E25 pin 7
*** Side 1 E13 pin 9
Jumpers:
E12 pin 9 to E22 pin 11
E26 pin 13 to E25 pin 7
E26 pin 8 to E40 pin 9
E26 pin 10 to PTH at left of E30 pin 8
E40 pin 10 to E36 pin 3
*** E26 pin 13 to E13 pion 9
NOTE: Tech revision F boards are reworked from CS revision P
to R. Etch revision C board are reworked from CS reivions M2
to M3.
M8109-C015A CODE: F APR-74 [FCO]
Problem: ECO (sic) M8109-C0015 rework procedure for revision F
is not complete. Timing stops in T5, will not run any diagnostics.
Correction: Add to rework procedure. (ed. I have noted the changes
with *** on M8109-C0015, above.)
M8109-D0016 CODE: F CS: S MAY-74 [FCO]
Problem: There is a shortage of 74S74-45 ICs #19-10950.
Correction: Allow the replacement of 74S74-45 with 74S74
#19-10544. The rework procedure for field use is as follows:
FOR ETCH REVISION C:
If E6 (?) E34 or E42 must be replaced, use part #19-10544. If
E8 or E15 must be replaced, proceed as follows:
Etch revision C never had jumpers W5 and W6 which changes a single
to a double suyncrhonizer, as indicated on certain CS revisions.
For a double-synchronizer, FCO M8109-C0013 must be installed. If
it is not already installed, thenproceed to isntall it.
While adding FCO M8100-C0013 replace E8, or E15 with #19-10544
instead of #19-10950.
FOR ETCH REVISION F:
Replace E6, E26 or E27 with part #19-10544 as is necessary due to
failure. Insure that jumper W5 is inserted and W6 is removed.
NOTE: The 74S74-45 and 74S74-50 ICs are no longer avilable and 74S74
must be used. In order for the circuit to continue to work, the
single rank synchronization must be converted to double rank.
In the event of failure of a 74S74-45 IC rework etch revision C boards
to CS revision M4 and etch revisiion F boards to CS revision S.
M8109-S0017 CODE: F CS: M5 and T [FCO] NOV-75
Problem: Spurious T1 through T5 clock pulses occur while margining +5V
and/or -15V for the M8109 module, which can cause CPU, FP11 and/or
KT11-C problems.
Correction: Modify the M8109 timing generator to increase +5V and/or
-15V margins. Resistors R1 thru R5 are changed from 4.7K to 3K ohms
#13-00432. Diodes D51 and D52 are deleted and D51 is replaced by a
33 (could be .33?) ohm 1/4W 5% resistor, 13-00197
When symptoms are present rework etch revision C M8109s from CS revision
M4 to M5. Rework Etch Revision F from CS revision S to T.
Quick check: D51, D52 deleted; 33 ohm resistor has replaced D51.
M8110: There are numerous ECOs/FCOs culminating in replacement by M8120.
Contact cube1us@gmail.com and I could lend out a DEC-O-LOG